r8a774a1.dtsi (5b971c71dd64c08c73c37f754f60a7d777ea70e9) r8a774a1.dtsi (da245a5066aa4c96c153a4ede3dab68d6b2306e8)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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1677 * clkout : #clock-cells = <0>; <&rcar_sound>;
1678 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1679 */
1680 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
1681 reg = <0 0xec500000 0 0x1000>, /* SCU */
1682 <0 0xec5a0000 0 0x100>, /* ADG */
1683 <0 0xec540000 0 0x1000>, /* SSIU */
1684 <0 0xec541000 0 0x280>, /* SSI */
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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1677 * clkout : #clock-cells = <0>; <&rcar_sound>;
1678 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1679 */
1680 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
1681 reg = <0 0xec500000 0 0x1000>, /* SCU */
1682 <0 0xec5a0000 0 0x100>, /* ADG */
1683 <0 0xec540000 0 0x1000>, /* SSIU */
1684 <0 0xec541000 0 0x280>, /* SSI */
1685 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1685 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1686 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1687
1688 clocks = <&cpg CPG_MOD 1005>,
1689 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1690 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1691 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1692 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1693 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,

--- 893 unchanged lines hidden --- 		1686 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1687
1688 clocks = <&cpg CPG_MOD 1005>,
1689 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1690 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1691 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1692 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1693 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,

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