r8a774a1.dtsi (391dca2105c435a2003c3c19f2d0b68742f43434) r8a774a1.dtsi (c4f223b419ba3fe44822d3180d3b9e5e6cb33c2e)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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2038 reg = <7>;
2039 remote-endpoint = <&vin7csi40>;
2040 };
2041 };
2042
2043 };
2044 };
2045
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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2038 reg = <7>;
2039 remote-endpoint = <&vin7csi40>;
2040 };
2041 };
2042
2043 };
2044 };
2045
2046 du: display@feb00000 {
2047 compatible = "renesas,du-r8a774a1";
2048 reg = <0 0xfeb00000 0 0x70000>;
2049 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2050 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2051 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2052 clocks = <&cpg CPG_MOD 724>,
2053 <&cpg CPG_MOD 723>,
2054 <&cpg CPG_MOD 722>;
2055 clock-names = "du.0", "du.1", "du.2";
2056 status = "disabled";
2057
2058 vsps = <&vspd0 &vspd1 &vspd2>;
2059
2060 ports {
2061 #address-cells = <1>;
2062 #size-cells = <0>;
2063
2064 port@0 {
2065 reg = <0>;
2066 du_out_rgb: endpoint {
2067 };
2068 };
2069 port@1 {
2070 reg = <1>;
2071 du_out_hdmi0: endpoint {
2072 };
2073 };
2074 port@2 {
2075 reg = <2>;
2076 du_out_lvds0: endpoint {
2077 remote-endpoint = <&lvds0_in>;
2078 };
2079 };
2080 };
2081 };
2082
2083 lvds0: lvds@feb90000 {
2084 compatible = "renesas,r8a774a1-lvds";
2085 reg = <0 0xfeb90000 0 0x14>;
2086 clocks = <&cpg CPG_MOD 727>;
2087 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2088 resets = <&cpg 727>;
2089 status = "disabled";
2090
2091 ports {
2092 #address-cells = <1>;
2093 #size-cells = <0>;
2094
2095 port@0 {
2096 reg = <0>;
2097 lvds0_in: endpoint {
2098 remote-endpoint = <&du_out_lvds0>;
2099 };
2100 };
2101 port@1 {
2102 reg = <1>;
2103 lvds0_out: endpoint {
2104 };
2105 };
2106 };
2107 };
2108
2046 prr: chipid@fff00044 {
2047 compatible = "renesas,prr";
2048 reg = <0 0xfff00044 0 4>;
2049 };
2050 };
2051
2052 thermal-zones {
2053 sensor_thermal1: sensor-thermal1 {

--- 64 unchanged lines hidden --- 		2109 prr: chipid@fff00044 {
2110 compatible = "renesas,prr";
2111 reg = <0 0xfff00044 0 4>;
2112 };
2113 };
2114
2115 thermal-zones {
2116 sensor_thermal1: sensor-thermal1 {

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