r8a774a1.dtsi (320424c7d44f54c18df9812fd7c45f6963524002) r8a774a1.dtsi (a636d8037ef6028a5a285acdfbfa35a488b6f9db)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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20 aliases {
21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
24 i2c3 = &i2c3;
25 i2c4 = &i2c4;
26 i2c5 = &i2c5;
27 i2c6 = &i2c6;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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20 aliases {
21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
24 i2c3 = &i2c3;
25 i2c4 = &i2c4;
26 i2c5 = &i2c5;
27 i2c6 = &i2c6;
28 i2c7 = &i2c_dvfs;
28 i2c7 = &iic_pmic;
29 };
30
31 /*
32 * The external audio clocks are configured as 0 Hz fixed frequency
33 * clocks by default.
34 * Boards that provide audio clocks should override them.
35 */
36 audio_clk_a: audio_clk_a {

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71 opp-hz = /bits/ 64 <1000000000>;
72 opp-microvolt = <820000>;
73 clock-latency-ns = <300000>;
74 };
75 opp-1500000000 {
76 opp-hz = /bits/ 64 <1500000000>;
77 opp-microvolt = <820000>;
78 clock-latency-ns = <300000>;
29 };
30
31 /*
32 * The external audio clocks are configured as 0 Hz fixed frequency
33 * clocks by default.
34 * Boards that provide audio clocks should override them.
35 */
36 audio_clk_a: audio_clk_a {

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71 opp-hz = /bits/ 64 <1000000000>;
72 opp-microvolt = <820000>;
73 clock-latency-ns = <300000>;
74 };
75 opp-1500000000 {
76 opp-hz = /bits/ 64 <1500000000>;
77 opp-microvolt = <820000>;
78 clock-latency-ns = <300000>;
79 opp-suspend;
79 };
80 };
81
82 cluster1_opp: opp_table1 {
83 compatible = "operating-points-v2";
84 opp-shared;
85
86 opp-800000000 {

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709 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
710 resets = <&cpg 918>;
711 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
712 dma-names = "tx", "rx";
713 i2c-scl-internal-delay-ns = <6>;
714 status = "disabled";
715 };
716
80 };
81 };
82
83 cluster1_opp: opp_table1 {
84 compatible = "operating-points-v2";
85 opp-shared;
86
87 opp-800000000 {

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710 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
711 resets = <&cpg 918>;
712 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
713 dma-names = "tx", "rx";
714 i2c-scl-internal-delay-ns = <6>;
715 status = "disabled";
716 };
717
717 i2c_dvfs: i2c@e60b0000 {
718 iic_pmic: i2c@e60b0000 {
718 #address-cells = <1>;
719 #size-cells = <0>;
720 compatible = "renesas,iic-r8a774a1",
721 "renesas,rcar-gen3-iic",
722 "renesas,rmobile-iic";
723 reg = <0 0xe60b0000 0 0x425>;
724 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&cpg CPG_MOD 926>;

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1122 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1123 "ch4", "ch5", "ch6", "ch7",
1124 "ch8", "ch9", "ch10", "ch11",
1125 "ch12", "ch13", "ch14", "ch15",
1126 "ch16", "ch17", "ch18", "ch19",
1127 "ch20", "ch21", "ch22", "ch23",
1128 "ch24";
1129 clocks = <&cpg CPG_MOD 812>;
719 #address-cells = <1>;
720 #size-cells = <0>;
721 compatible = "renesas,iic-r8a774a1",
722 "renesas,rcar-gen3-iic",
723 "renesas,rmobile-iic";
724 reg = <0 0xe60b0000 0 0x425>;
725 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&cpg CPG_MOD 926>;

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1123 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1124 "ch4", "ch5", "ch6", "ch7",
1125 "ch8", "ch9", "ch10", "ch11",
1126 "ch12", "ch13", "ch14", "ch15",
1127 "ch16", "ch17", "ch18", "ch19",
1128 "ch20", "ch21", "ch22", "ch23",
1129 "ch24";
1130 clocks = <&cpg CPG_MOD 812>;
1131 clock-names = "fck";
1130 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1131 resets = <&cpg 812>;
1132 phy-mode = "rgmii";
1133 rx-internal-delay-ps = <0>;
1134 tx-internal-delay-ps = <0>;
1135 iommus = <&ipmmu_ds0 16>;
1136 #address-cells = <1>;
1137 #size-cells = <0>;

--- 1732 unchanged lines hidden --- 		1132 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1133 resets = <&cpg 812>;
1134 phy-mode = "rgmii";
1135 rx-internal-delay-ps = <0>;
1136 tx-internal-delay-ps = <0>;
1137 iommus = <&ipmmu_ds0 16>;
1138 #address-cells = <1>;
1139 #size-cells = <0>;

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