r8a774a1.dtsi (0aab5b914b41601ee7e4ba9bd81344665db1fbca) r8a774a1.dtsi (9504a9f27a8c2c3a78f566c5cde75b53657b386a)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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2318 pciec0: pcie@fe000000 {
2319 compatible = "renesas,pcie-r8a774a1",
2320 "renesas,pcie-rcar-gen3";
2321 reg = <0 0xfe000000 0 0x80000>;
2322 #address-cells = <3>;
2323 #size-cells = <2>;
2324 bus-range = <0x00 0xff>;
2325 device_type = "pci";
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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2318 pciec0: pcie@fe000000 {
2319 compatible = "renesas,pcie-r8a774a1",
2320 "renesas,pcie-rcar-gen3";
2321 reg = <0 0xfe000000 0 0x80000>;
2322 #address-cells = <3>;
2323 #size-cells = <2>;
2324 bus-range = <0x00 0xff>;
2325 device_type = "pci";
2326 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
2327 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
2328 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
2329 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2326 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2327 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2328 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2329 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2330 /* Map all possible DDR as inbound ranges */
2331 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2332 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2333 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2334 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2335 #interrupt-cells = <1>;
2336 interrupt-map-mask = <0 0 0 0>;
2337 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

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2345 pciec1: pcie@ee800000 {
2346 compatible = "renesas,pcie-r8a774a1",
2347 "renesas,pcie-rcar-gen3";
2348 reg = <0 0xee800000 0 0x80000>;
2349 #address-cells = <3>;
2350 #size-cells = <2>;
2351 bus-range = <0x00 0xff>;
2352 device_type = "pci";
2330 /* Map all possible DDR as inbound ranges */
2331 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2332 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2333 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2334 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2335 #interrupt-cells = <1>;
2336 interrupt-map-mask = <0 0 0 0>;
2337 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

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2345 pciec1: pcie@ee800000 {
2346 compatible = "renesas,pcie-r8a774a1",
2347 "renesas,pcie-rcar-gen3";
2348 reg = <0 0xee800000 0 0x80000>;
2349 #address-cells = <3>;
2350 #size-cells = <2>;
2351 bus-range = <0x00 0xff>;
2352 device_type = "pci";
2353 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
2354 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
2355 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
2356 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2353 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2354 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2355 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2356 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2357 /* Map all possible DDR as inbound ranges */
2358 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2359 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2360 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2361 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2362 #interrupt-cells = <1>;
2363 interrupt-map-mask = <0 0 0 0>;
2364 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

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2357 /* Map all possible DDR as inbound ranges */
2358 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2359 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2360 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2361 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2362 #interrupt-cells = <1>;
2363 interrupt-map-mask = <0 0 0 0>;
2364 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

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