r8a774a1.dtsi (03abfdd31c66f0ecd629a1d1362e87551ce6c027) r8a774a1.dtsi (721b76195b31467e56851fbab3855e700f281270)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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2629 };
2630
2631 du: display@feb00000 {
2632 compatible = "renesas,du-r8a774a1";
2633 reg = <0 0xfeb00000 0 0x70000>;
2634 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2635 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2636 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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2629 };
2630
2631 du: display@feb00000 {
2632 compatible = "renesas,du-r8a774a1";
2633 reg = <0 0xfeb00000 0 0x70000>;
2634 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2635 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2636 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2637 clocks = <&cpg CPG_MOD 724>,
2638 <&cpg CPG_MOD 723>,
2637 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2639 <&cpg CPG_MOD 722>;
2640 clock-names = "du.0", "du.1", "du.2";
2638 <&cpg CPG_MOD 722>;
2639 clock-names = "du.0", "du.1", "du.2";
2640 resets = <&cpg 724>, <&cpg 722>;
2641 reset-names = "du.0", "du.2";
2641 status = "disabled";
2642
2643 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2644
2645 ports {
2646 #address-cells = <1>;
2647 #size-cells = <0>;
2648

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2643
2644 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2645
2646 ports {
2647 #address-cells = <1>;
2648 #size-cells = <0>;
2649

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