ebisu.dtsi (03ab8e6297acd1bc0eedaa050e2a1635c576fd11) ebisu.dtsi (5cf12ac9493ae2603e5ba27c1040a88c7b26dd28)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Ebisu board
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>

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140 };
141
142 memory@48000000 {
143 device_type = "memory";
144 /* first 128MB is reserved for secure area. */
145 reg = <0x0 0x48000000 0x0 0x38000000>;
146 };
147
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Ebisu board
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>

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140 };
141
142 memory@48000000 {
143 device_type = "memory";
144 /* first 128MB is reserved for secure area. */
145 reg = <0x0 0x48000000 0x0 0x38000000>;
146 };
147
148 reg_1p8v: regulator0 {
148 reg_1p8v: regulator-1p8v {
149 compatible = "regulator-fixed";
150 regulator-name = "fixed-1.8V";
151 regulator-min-microvolt = <1800000>;
152 regulator-max-microvolt = <1800000>;
153 regulator-boot-on;
154 regulator-always-on;
155 };
156
149 compatible = "regulator-fixed";
150 regulator-name = "fixed-1.8V";
151 regulator-min-microvolt = <1800000>;
152 regulator-max-microvolt = <1800000>;
153 regulator-boot-on;
154 regulator-always-on;
155 };
156
157 reg_3p3v: regulator1 {
157 reg_3p3v: regulator-3p3v {
158 compatible = "regulator-fixed";
159 regulator-name = "fixed-3.3V";
160 regulator-min-microvolt = <3300000>;
161 regulator-max-microvolt = <3300000>;
162 regulator-boot-on;
163 regulator-always-on;
164 };
165
158 compatible = "regulator-fixed";
159 regulator-name = "fixed-3.3V";
160 regulator-min-microvolt = <3300000>;
161 regulator-max-microvolt = <3300000>;
162 regulator-boot-on;
163 regulator-always-on;
164 };
165
166 reg_12p0v: regulator2 {
166 reg_12p0v: regulator-12p0v {
167 compatible = "regulator-fixed";
168 regulator-name = "D12.0V";
169 regulator-min-microvolt = <12000000>;
170 regulator-max-microvolt = <12000000>;
171 regulator-boot-on;
172 regulator-always-on;
173 };
174

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351
352 clocks = <&cpg CPG_MOD 724>,
353 <&cpg CPG_MOD 723>,
354 <&x13_clk>;
355 clock-names = "du.0", "du.1", "dclkin.0";
356
357 ports {
358 port@0 {
167 compatible = "regulator-fixed";
168 regulator-name = "D12.0V";
169 regulator-min-microvolt = <12000000>;
170 regulator-max-microvolt = <12000000>;
171 regulator-boot-on;
172 regulator-always-on;
173 };
174

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351
352 clocks = <&cpg CPG_MOD 724>,
353 <&cpg CPG_MOD 723>,
354 <&x13_clk>;
355 clock-names = "du.0", "du.1", "dclkin.0";
356
357 ports {
358 port@0 {
359 endpoint {
359 du_out_rgb: endpoint {
360 remote-endpoint = <&adv7123_in>;
361 };
362 };
363 };
364};
365
366&ehci0 {
367 dr_mode = "otg";

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595 function = "pwm3";
596 };
597
598 pwm5_pins: pwm5 {
599 groups = "pwm5_a";
600 function = "pwm5";
601 };
602
360 remote-endpoint = <&adv7123_in>;
361 };
362 };
363 };
364};
365
366&ehci0 {
367 dr_mode = "otg";

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595 function = "pwm3";
596 };
597
598 pwm5_pins: pwm5 {
599 groups = "pwm5_a";
600 function = "pwm5";
601 };
602
603 rpc_pins: rpc {
604 groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
605 "rpc_int";
606 function = "rpc";
607 };
608
603 scif2_pins: scif2 {
604 groups = "scif2_data_a";
605 function = "scif2";
606 };
607
608 sdhi0_pins: sd0 {
609 groups = "sdhi0_data4", "sdhi0_ctrl";
610 function = "sdhi0";

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706 dai0 {
707 playback = <&ssi0>, <&src0>, <&dvc0>;
708 capture = <&ssi1>, <&src1>, <&dvc1>;
709 };
710 };
711
712};
713
609 scif2_pins: scif2 {
610 groups = "scif2_data_a";
611 function = "scif2";
612 };
613
614 sdhi0_pins: sd0 {
615 groups = "sdhi0_data4", "sdhi0_ctrl";
616 function = "sdhi0";

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712 dai0 {
713 playback = <&ssi0>, <&src0>, <&dvc0>;
714 capture = <&ssi1>, <&src1>, <&dvc1>;
715 };
716 };
717
718};
719
720&rpc {
721 pinctrl-0 = <&rpc_pins>;
722 pinctrl-names = "default";
723
724 /* Left disabled. To be enabled by firmware when unlocked. */
725
726 flash@0 {
727 compatible = "cypress,hyperflash", "cfi-flash";
728 reg = <0>;
729
730 partitions {
731 compatible = "fixed-partitions";
732 #address-cells = <1>;
733 #size-cells = <1>;
734
735 bootparam@0 {
736 reg = <0x00000000 0x040000>;
737 read-only;
738 };
739 bl2@40000 {
740 reg = <0x00040000 0x140000>;
741 read-only;
742 };
743 cert_header_sa6@180000 {
744 reg = <0x00180000 0x040000>;
745 read-only;
746 };
747 bl31@1c0000 {
748 reg = <0x001c0000 0x040000>;
749 read-only;
750 };
751 tee@200000 {
752 reg = <0x00200000 0x440000>;
753 read-only;
754 };
755 uboot@640000 {
756 reg = <0x00640000 0x100000>;
757 read-only;
758 };
759 dtb@740000 {
760 reg = <0x00740000 0x080000>;
761 };
762 kernel@7c0000 {
763 reg = <0x007c0000 0x1400000>;
764 };
765 user@1bc0000 {
766 reg = <0x01bc0000 0x2440000>;
767 };
768 };
769 };
770};
771
714&rwdt {
715 timeout-sec = <60>;
716 status = "okay";
717};
718
719&scif2 {
720 pinctrl-0 = <&scif2_pins>;
721 pinctrl-names = "default";

--- 82 unchanged lines hidden --- 		772&rwdt {
773 timeout-sec = <60>;
774 status = "okay";
775};
776
777&scif2 {
778 pinctrl-0 = <&scif2_pins>;
779 pinctrl-names = "default";

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