sm8250.dtsi (e7173009e139bc13bf7833ea4185dda4779b95f3) sm8250.dtsi (8d5fd4e4d4e3c128d5afa925bf98c98e66a5205b)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8#include <dt-bindings/clock/qcom,gcc-sm8250.h>

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13#include <dt-bindings/interconnect/qcom,osm-l3.h>
14#include <dt-bindings/interconnect/qcom,sm8250.h>
15#include <dt-bindings/mailbox/qcom-ipcc.h>
16#include <dt-bindings/power/qcom-rpmpd.h>
17#include <dt-bindings/soc/qcom,apr.h>
18#include <dt-bindings/soc/qcom,rpmh-rsc.h>
19#include <dt-bindings/sound/qcom,q6afe.h>
20#include <dt-bindings/thermal/thermal.h>
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8#include <dt-bindings/clock/qcom,gcc-sm8250.h>

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13#include <dt-bindings/interconnect/qcom,osm-l3.h>
14#include <dt-bindings/interconnect/qcom,sm8250.h>
15#include <dt-bindings/mailbox/qcom-ipcc.h>
16#include <dt-bindings/power/qcom-rpmpd.h>
17#include <dt-bindings/soc/qcom,apr.h>
18#include <dt-bindings/soc/qcom,rpmh-rsc.h>
19#include <dt-bindings/sound/qcom,q6afe.h>
20#include <dt-bindings/thermal/thermal.h>
21#include <dt-bindings/clock/qcom,camcc-sm8250.h>
22#include <dt-bindings/clock/qcom,videocc-sm8250.h>
23
24/ {
25 interrupt-parent = <&intc>;
26
27 #address-cells = <2>;
28 #size-cells = <2>;
29

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2986 #address-cells = <2>;
2987 #size-cells = <2>;
2988 ranges;
2989 dma-ranges;
2990
2991 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2992 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2993 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
21#include <dt-bindings/clock/qcom,videocc-sm8250.h>
22
23/ {
24 interrupt-parent = <&intc>;
25
26 #address-cells = <2>;
27 #size-cells = <2>;
28

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2985 #address-cells = <2>;
2986 #size-cells = <2>;
2987 ranges;
2988 dma-ranges;
2989
2990 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2991 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2992 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2994 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2995 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2993 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2994 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2996 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2995 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2997 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2998 "sleep", "xo";
2996 clock-names = "cfg_noc",
2997 "core",
2998 "iface",
2999 "sleep",
3000 "mock_utmi",
3001 "xo";
2999
3000 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3001 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3002 assigned-clock-rates = <19200000>, <200000000>;
3003
3004 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3005 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3006 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,

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3037 #address-cells = <2>;
3038 #size-cells = <2>;
3039 ranges;
3040 dma-ranges;
3041
3042 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3043 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3044 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3002
3003 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3004 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3005 assigned-clock-rates = <19200000>, <200000000>;
3006
3007 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3008 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3009 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,

--- 30 unchanged lines hidden (view full) ---

3040 #address-cells = <2>;
3041 #size-cells = <2>;
3042 ranges;
3043 dma-ranges;
3044
3045 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3046 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3047 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3045 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3046 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3048 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3049 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3047 <&gcc GCC_USB3_SEC_CLKREF_EN>;
3050 <&gcc GCC_USB3_SEC_CLKREF_EN>;
3048 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3049 "sleep", "xo";
3051 clock-names = "cfg_noc",
3052 "core",
3053 "iface",
3054 "sleep",
3055 "mock_utmi",
3056 "xo";
3050
3051 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3052 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3053 assigned-clock-rates = <19200000>, <200000000>;
3054
3055 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3056 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
3057 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,

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3145 power-domains = <&rpmhpd SM8250_MMCX>;
3146 required-opps = <&rpmhpd_opp_low_svs>;
3147 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
3148 #clock-cells = <1>;
3149 #reset-cells = <1>;
3150 #power-domain-cells = <1>;
3151 };
3152
3057
3058 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3059 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3060 assigned-clock-rates = <19200000>, <200000000>;
3061
3062 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3063 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
3064 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,

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3152 power-domains = <&rpmhpd SM8250_MMCX>;
3153 required-opps = <&rpmhpd_opp_low_svs>;
3154 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
3155 #clock-cells = <1>;
3156 #reset-cells = <1>;
3157 #power-domain-cells = <1>;
3158 };
3159
3153 cci0: cci@ac4f000 {
3154 compatible = "qcom,sm8250-cci";
3155 #address-cells = <1>;
3156 #size-cells = <0>;
3157
3158 reg = <0 0x0ac4f000 0 0x1000>;
3159 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
3160 power-domains = <&camcc TITAN_TOP_GDSC>;
3161
3162 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3163 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3164 <&camcc CAM_CC_CPAS_AHB_CLK>,
3165 <&camcc CAM_CC_CCI_0_CLK>,
3166 <&camcc CAM_CC_CCI_0_CLK_SRC>;
3167 clock-names = "camnoc_axi",
3168 "slow_ahb_src",
3169 "cpas_ahb",
3170 "cci",
3171 "cci_src";
3172
3173 pinctrl-0 = <&cci0_default>;
3174 pinctrl-1 = <&cci0_sleep>;
3175 pinctrl-names = "default", "sleep";
3176
3177 status = "disabled";
3178
3179 cci0_i2c0: i2c-bus@0 {
3180 reg = <0>;
3181 clock-frequency = <1000000>;
3182 #address-cells = <1>;
3183 #size-cells = <0>;
3184 };
3185
3186 cci0_i2c1: i2c-bus@1 {
3187 reg = <1>;
3188 clock-frequency = <1000000>;
3189 #address-cells = <1>;
3190 #size-cells = <0>;
3191 };
3192 };
3193
3194 cci1: cci@ac50000 {
3195 compatible = "qcom,sm8250-cci";
3196 #address-cells = <1>;
3197 #size-cells = <0>;
3198
3199 reg = <0 0x0ac50000 0 0x1000>;
3200 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
3201 power-domains = <&camcc TITAN_TOP_GDSC>;
3202
3203 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3204 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3205 <&camcc CAM_CC_CPAS_AHB_CLK>,
3206 <&camcc CAM_CC_CCI_1_CLK>,
3207 <&camcc CAM_CC_CCI_1_CLK_SRC>;
3208 clock-names = "camnoc_axi",
3209 "slow_ahb_src",
3210 "cpas_ahb",
3211 "cci",
3212 "cci_src";
3213
3214 pinctrl-0 = <&cci1_default>;
3215 pinctrl-1 = <&cci1_sleep>;
3216 pinctrl-names = "default", "sleep";
3217
3218 status = "disabled";
3219
3220 cci1_i2c0: i2c-bus@0 {
3221 reg = <0>;
3222 clock-frequency = <1000000>;
3223 #address-cells = <1>;
3224 #size-cells = <0>;
3225 };
3226
3227 cci1_i2c1: i2c-bus@1 {
3228 reg = <1>;
3229 clock-frequency = <1000000>;
3230 #address-cells = <1>;
3231 #size-cells = <0>;
3232 };
3233 };
3234
3235 camss: camss@ac6a000 {
3236 compatible = "qcom,sm8250-camss";
3237 status = "disabled";
3238
3239 reg = <0 0xac6a000 0 0x2000>,
3240 <0 0xac6c000 0 0x2000>,
3241 <0 0xac6e000 0 0x1000>,
3242 <0 0xac70000 0 0x1000>,
3243 <0 0xac72000 0 0x1000>,
3244 <0 0xac74000 0 0x1000>,
3245 <0 0xacb4000 0 0xd000>,
3246 <0 0xacc3000 0 0xd000>,
3247 <0 0xacd9000 0 0x2200>,
3248 <0 0xacdb200 0 0x2200>;
3249 reg-names = "csiphy0",
3250 "csiphy1",
3251 "csiphy2",
3252 "csiphy3",
3253 "csiphy4",
3254 "csiphy5",
3255 "vfe0",
3256 "vfe1",
3257 "vfe_lite0",
3258 "vfe_lite1";
3259
3260 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
3261 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
3262 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
3263 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
3264 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
3265 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
3266 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
3267 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
3268 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
3269 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
3270 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
3271 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
3272 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
3273 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
3274 interrupt-names = "csiphy0",
3275 "csiphy1",
3276 "csiphy2",
3277 "csiphy3",
3278 "csiphy4",
3279 "csiphy5",
3280 "csid0",
3281 "csid1",
3282 "csid2",
3283 "csid3",
3284 "vfe0",
3285 "vfe1",
3286 "vfe_lite0",
3287 "vfe_lite1";
3288
3289 power-domains = <&camcc IFE_0_GDSC>,
3290 <&camcc IFE_1_GDSC>,
3291 <&camcc TITAN_TOP_GDSC>;
3292
3293 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3294 <&gcc GCC_CAMERA_HF_AXI_CLK>,
3295 <&gcc GCC_CAMERA_SF_AXI_CLK>,
3296 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3297 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
3298 <&camcc CAM_CC_CORE_AHB_CLK>,
3299 <&camcc CAM_CC_CPAS_AHB_CLK>,
3300 <&camcc CAM_CC_CSIPHY0_CLK>,
3301 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
3302 <&camcc CAM_CC_CSIPHY1_CLK>,
3303 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
3304 <&camcc CAM_CC_CSIPHY2_CLK>,
3305 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
3306 <&camcc CAM_CC_CSIPHY3_CLK>,
3307 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
3308 <&camcc CAM_CC_CSIPHY4_CLK>,
3309 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
3310 <&camcc CAM_CC_CSIPHY5_CLK>,
3311 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
3312 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3313 <&camcc CAM_CC_IFE_0_AHB_CLK>,
3314 <&camcc CAM_CC_IFE_0_AXI_CLK>,
3315 <&camcc CAM_CC_IFE_0_CLK>,
3316 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
3317 <&camcc CAM_CC_IFE_0_CSID_CLK>,
3318 <&camcc CAM_CC_IFE_0_AREG_CLK>,
3319 <&camcc CAM_CC_IFE_1_AHB_CLK>,
3320 <&camcc CAM_CC_IFE_1_AXI_CLK>,
3321 <&camcc CAM_CC_IFE_1_CLK>,
3322 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
3323 <&camcc CAM_CC_IFE_1_CSID_CLK>,
3324 <&camcc CAM_CC_IFE_1_AREG_CLK>,
3325 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
3326 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
3327 <&camcc CAM_CC_IFE_LITE_CLK>,
3328 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
3329 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
3330
3331 clock-names = "cam_ahb_clk",
3332 "cam_hf_axi",
3333 "cam_sf_axi",
3334 "camnoc_axi",
3335 "camnoc_axi_src",
3336 "core_ahb",
3337 "cpas_ahb",
3338 "csiphy0",
3339 "csiphy0_timer",
3340 "csiphy1",
3341 "csiphy1_timer",
3342 "csiphy2",
3343 "csiphy2_timer",
3344 "csiphy3",
3345 "csiphy3_timer",
3346 "csiphy4",
3347 "csiphy4_timer",
3348 "csiphy5",
3349 "csiphy5_timer",
3350 "slow_ahb_src",
3351 "vfe0_ahb",
3352 "vfe0_axi",
3353 "vfe0",
3354 "vfe0_cphy_rx",
3355 "vfe0_csid",
3356 "vfe0_areg",
3357 "vfe1_ahb",
3358 "vfe1_axi",
3359 "vfe1",
3360 "vfe1_cphy_rx",
3361 "vfe1_csid",
3362 "vfe1_areg",
3363 "vfe_lite_ahb",
3364 "vfe_lite_axi",
3365 "vfe_lite",
3366 "vfe_lite_cphy_rx",
3367 "vfe_lite_csid";
3368
3369 iommus = <&apps_smmu 0x800 0x400>,
3370 <&apps_smmu 0x801 0x400>,
3371 <&apps_smmu 0x840 0x400>,
3372 <&apps_smmu 0x841 0x400>,
3373 <&apps_smmu 0xc00 0x400>,
3374 <&apps_smmu 0xc01 0x400>,
3375 <&apps_smmu 0xc40 0x400>,
3376 <&apps_smmu 0xc41 0x400>;
3377
3378 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
3379 <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
3380 <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
3381 <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
3382 interconnect-names = "cam_ahb",
3383 "cam_hf_0_mnoc",
3384 "cam_sf_0_mnoc",
3385 "cam_sf_icp_mnoc";
3386 };
3387
3388 camcc: clock-controller@ad00000 {
3389 compatible = "qcom,sm8250-camcc";
3390 reg = <0 0x0ad00000 0 0x10000>;
3391 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3392 <&rpmhcc RPMH_CXO_CLK>,
3393 <&rpmhcc RPMH_CXO_CLK_A>,
3394 <&sleep_clk>;
3395 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3396 power-domains = <&rpmhpd SM8250_MMCX>;
3397 required-opps = <&rpmhpd_opp_low_svs>;
3398 #clock-cells = <1>;
3399 #reset-cells = <1>;
3400 #power-domain-cells = <1>;
3401 };
3402
3403 mdss: mdss@ae00000 {
3404 compatible = "qcom,sm8250-mdss";
3405 reg = <0 0x0ae00000 0 0x1000>;
3406 reg-names = "mdss";
3407
3408 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
3409 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
3410 interconnect-names = "mdp0-mem", "mdp1-mem";

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3448 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3449 assigned-clock-rates = <460000000>,
3450 <19200000>;
3451
3452 operating-points-v2 = <&mdp_opp_table>;
3453 power-domains = <&rpmhpd SM8250_MMCX>;
3454
3455 interrupt-parent = <&mdss>;
3160 mdss: mdss@ae00000 {
3161 compatible = "qcom,sm8250-mdss";
3162 reg = <0 0x0ae00000 0 0x1000>;
3163 reg-names = "mdss";
3164
3165 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
3166 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
3167 interconnect-names = "mdp0-mem", "mdp1-mem";

--- 37 unchanged lines hidden (view full) ---

3205 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3206 assigned-clock-rates = <460000000>,
3207 <19200000>;
3208
3209 operating-points-v2 = <&mdp_opp_table>;
3210 power-domains = <&rpmhpd SM8250_MMCX>;
3211
3212 interrupt-parent = <&mdss>;
3456 interrupts = <0>;
3213 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
3457
3458 ports {
3459 #address-cells = <1>;
3460 #size-cells = <0>;
3461
3462 port@0 {
3463 reg = <0>;
3464 dpu_intf1_out: endpoint {

--- 35 unchanged lines hidden (view full) ---

3500 };
3501
3502 dsi0: dsi@ae94000 {
3503 compatible = "qcom,mdss-dsi-ctrl";
3504 reg = <0 0x0ae94000 0 0x400>;
3505 reg-names = "dsi_ctrl";
3506
3507 interrupt-parent = <&mdss>;
3214
3215 ports {
3216 #address-cells = <1>;
3217 #size-cells = <0>;
3218
3219 port@0 {
3220 reg = <0>;
3221 dpu_intf1_out: endpoint {

--- 35 unchanged lines hidden (view full) ---

3257 };
3258
3259 dsi0: dsi@ae94000 {
3260 compatible = "qcom,mdss-dsi-ctrl";
3261 reg = <0 0x0ae94000 0 0x400>;
3262 reg-names = "dsi_ctrl";
3263
3264 interrupt-parent = <&mdss>;
3508 interrupts = <4>;
3265 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
3509
3510 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3511 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3512 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3513 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3514 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3515 <&gcc GCC_DISP_HF_AXI_CLK>;
3516 clock-names = "byte",

--- 56 unchanged lines hidden (view full) ---

3573 };
3574
3575 dsi1: dsi@ae96000 {
3576 compatible = "qcom,mdss-dsi-ctrl";
3577 reg = <0 0x0ae96000 0 0x400>;
3578 reg-names = "dsi_ctrl";
3579
3580 interrupt-parent = <&mdss>;
3266
3267 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3268 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3269 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3270 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3271 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3272 <&gcc GCC_DISP_HF_AXI_CLK>;
3273 clock-names = "byte",

--- 56 unchanged lines hidden (view full) ---

3330 };
3331
3332 dsi1: dsi@ae96000 {
3333 compatible = "qcom,mdss-dsi-ctrl";
3334 reg = <0 0x0ae96000 0 0x400>;
3335 reg-names = "dsi_ctrl";
3336
3337 interrupt-parent = <&mdss>;
3581 interrupts = <5>;
3338 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
3582
3583 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3584 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3585 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3586 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3587 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3588 <&gcc GCC_DISP_HF_AXI_CLK>;
3589 clock-names = "byte",

--- 175 unchanged lines hidden (view full) ---

3765 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3766 gpio-controller;
3767 #gpio-cells = <2>;
3768 interrupt-controller;
3769 #interrupt-cells = <2>;
3770 gpio-ranges = <&tlmm 0 0 181>;
3771 wakeup-parent = <&pdc>;
3772
3339
3340 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3341 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3342 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3343 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3344 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3345 <&gcc GCC_DISP_HF_AXI_CLK>;
3346 clock-names = "byte",

--- 175 unchanged lines hidden (view full) ---

3522 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3523 gpio-controller;
3524 #gpio-cells = <2>;
3525 interrupt-controller;
3526 #interrupt-cells = <2>;
3527 gpio-ranges = <&tlmm 0 0 181>;
3528 wakeup-parent = <&pdc>;
3529
3773 cci0_default: cci0-default {
3774 cci0_i2c0_default: cci0-i2c0-default {
3775 /* SDA, SCL */
3776 pins = "gpio101", "gpio102";
3777 function = "cci_i2c";
3778
3779 bias-pull-up;
3780 drive-strength = <2>; /* 2 mA */
3781 };
3782
3783 cci0_i2c1_default: cci0-i2c1-default {
3784 /* SDA, SCL */
3785 pins = "gpio103", "gpio104";
3786 function = "cci_i2c";
3787
3788 bias-pull-up;
3789 drive-strength = <2>; /* 2 mA */
3790 };
3791 };
3792
3793 cci0_sleep: cci0-sleep {
3794 cci0_i2c0_sleep: cci0-i2c0-sleep {
3795 /* SDA, SCL */
3796 pins = "gpio101", "gpio102";
3797 function = "cci_i2c";
3798
3799 drive-strength = <2>; /* 2 mA */
3800 bias-pull-down;
3801 };
3802
3803 cci0_i2c1_sleep: cci0-i2c1-sleep {
3804 /* SDA, SCL */
3805 pins = "gpio103", "gpio104";
3806 function = "cci_i2c";
3807
3808 drive-strength = <2>; /* 2 mA */
3809 bias-pull-down;
3810 };
3811 };
3812
3813 cci1_default: cci1-default {
3814 cci1_i2c0_default: cci1-i2c0-default {
3815 /* SDA, SCL */
3816 pins = "gpio105","gpio106";
3817 function = "cci_i2c";
3818
3819 bias-pull-up;
3820 drive-strength = <2>; /* 2 mA */
3821 };
3822
3823 cci1_i2c1_default: cci1-i2c1-default {
3824 /* SDA, SCL */
3825 pins = "gpio107","gpio108";
3826 function = "cci_i2c";
3827
3828 bias-pull-up;
3829 drive-strength = <2>; /* 2 mA */
3830 };
3831 };
3832
3833 cci1_sleep: cci1-sleep {
3834 cci1_i2c0_sleep: cci1-i2c0-sleep {
3835 /* SDA, SCL */
3836 pins = "gpio105","gpio106";
3837 function = "cci_i2c";
3838
3839 bias-pull-down;
3840 drive-strength = <2>; /* 2 mA */
3841 };
3842
3843 cci1_i2c1_sleep: cci1-i2c1-sleep {
3844 /* SDA, SCL */
3845 pins = "gpio107","gpio108";
3846 function = "cci_i2c";
3847
3848 bias-pull-down;
3849 drive-strength = <2>; /* 2 mA */
3850 };
3851 };
3852
3853 pri_mi2s_active: pri-mi2s-active {
3854 sclk {
3855 pins = "gpio138";
3856 function = "mi2s0_sck";
3857 drive-strength = <8>;
3858 bias-disable;
3859 };
3860

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4980 };
4981
4982 rpmhpd_opp_turbo_l1: opp10 {
4983 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4984 };
4985 };
4986 };
4987
3530 pri_mi2s_active: pri-mi2s-active {
3531 sclk {
3532 pins = "gpio138";
3533 function = "mi2s0_sck";
3534 drive-strength = <8>;
3535 bias-disable;
3536 };
3537

--- 1119 unchanged lines hidden (view full) ---

4657 };
4658
4659 rpmhpd_opp_turbo_l1: opp10 {
4660 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4661 };
4662 };
4663 };
4664
4988 apps_bcm_voter: bcm-voter {
4665 apps_bcm_voter: bcm_voter {
4989 compatible = "qcom,bcm-voter";
4990 };
4991 };
4992
4993 epss_l3: interconnect@18590000 {
4994 compatible = "qcom,sm8250-epss-l3";
4995 reg = <0 0x18590000 0 0x1000>;
4996

--- 771 unchanged lines hidden --- 		4666 compatible = "qcom,bcm-voter";
4667 };
4668 };
4669
4670 epss_l3: interconnect@18590000 {
4671 compatible = "qcom,sm8250-epss-l3";
4672 reg = <0 0x18590000 0 0x1000>;
4673

--- 771 unchanged lines hidden ---