sm6350.dtsi (fc0e7dd6d2e2c9f8b2c6497a190ee29d8f3aef3a) sm6350.dtsi (8d5fd4e4d4e3c128d5afa925bf98c98e66a5205b)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
4 */
5
6#include <dt-bindings/clock/qcom,gcc-sm6350.h>
7#include <dt-bindings/clock/qcom,rpmh.h>
8#include <dt-bindings/gpio/gpio.h>

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512
513 opp-384000000 {
514 opp-hz = /bits/ 64 <384000000>;
515 required-opps = <&rpmhpd_opp_svs_l1>;
516 };
517 };
518 };
519
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
4 */
5
6#include <dt-bindings/clock/qcom,gcc-sm6350.h>
7#include <dt-bindings/clock/qcom,rpmh.h>
8#include <dt-bindings/gpio/gpio.h>

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512
513 opp-384000000 {
514 opp-hz = /bits/ 64 <384000000>;
515 required-opps = <&rpmhpd_opp_svs_l1>;
516 };
517 };
518 };
519
520 qupv3_id_0: geniqup@8c0000 {
521 compatible = "qcom,geni-se-qup";
522 reg = <0x0 0x8c0000 0x0 0x2000>;
523 clock-names = "m-ahb", "s-ahb";
524 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
525 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
526 #address-cells = <2>;
527 #size-cells = <2>;
528 iommus = <&apps_smmu 0x43 0x0>;
529 ranges;
530 status = "disabled";
531
532 i2c0: i2c@880000 {
533 compatible = "qcom,geni-i2c";
534 reg = <0 0x00880000 0 0x4000>;
535 clock-names = "se";
536 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
537 pinctrl-names = "default";
538 pinctrl-0 = <&qup_i2c0_default>;
539 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
540 #address-cells = <1>;
541 #size-cells = <0>;
542 status = "disabled";
543 };
544
545 i2c2: i2c@888000 {
546 compatible = "qcom,geni-i2c";
547 reg = <0 0x00888000 0 0x4000>;
548 clock-names = "se";
549 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&qup_i2c2_default>;
552 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 status = "disabled";
556 };
557 };
558
559 qupv3_id_1: geniqup@9c0000 {
560 compatible = "qcom,geni-se-qup";
561 reg = <0x0 0x9c0000 0x0 0x2000>;
562 clock-names = "m-ahb", "s-ahb";
563 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
564 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
565 #address-cells = <2>;
566 #size-cells = <2>;
567 iommus = <&apps_smmu 0x4c3 0x0>;
568 ranges;
569 status = "disabled";
570
520 qupv3_id_1: geniqup@9c0000 {
521 compatible = "qcom,geni-se-qup";
522 reg = <0x0 0x9c0000 0x0 0x2000>;
523 clock-names = "m-ahb", "s-ahb";
524 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
525 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
526 #address-cells = <2>;
527 #size-cells = <2>;
528 iommus = <&apps_smmu 0x4c3 0x0>;
529 ranges;
530 status = "disabled";
531
571 i2c6: i2c@980000 {
572 compatible = "qcom,geni-i2c";
573 reg = <0 0x00980000 0 0x4000>;
574 clock-names = "se";
575 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&qup_i2c6_default>;
578 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
579 #address-cells = <1>;
580 #size-cells = <0>;
581 status = "disabled";
582 };
583
584 i2c7: i2c@984000 {
585 compatible = "qcom,geni-i2c";
586 reg = <0 0x00984000 0 0x4000>;
587 clock-names = "se";
588 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
589 pinctrl-names = "default";
590 pinctrl-0 = <&qup_i2c7_default>;
591 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
592 #address-cells = <1>;
593 #size-cells = <0>;
594 status = "disabled";
595 };
596
597 i2c8: i2c@988000 {
598 compatible = "qcom,geni-i2c";
599 reg = <0 0x00988000 0 0x4000>;
600 clock-names = "se";
601 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
602 pinctrl-names = "default";
603 pinctrl-0 = <&qup_i2c8_default>;
604 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
605 #address-cells = <1>;
606 #size-cells = <0>;
607 status = "disabled";
608 };
609
610 uart9: serial@98c000 {
532 uart2: serial@98c000 {
611 compatible = "qcom,geni-debug-uart";
612 reg = <0 0x98c000 0 0x4000>;
613 clock-names = "se";
614 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
615 pinctrl-names = "default";
533 compatible = "qcom,geni-debug-uart";
534 reg = <0 0x98c000 0 0x4000>;
535 clock-names = "se";
536 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
537 pinctrl-names = "default";
616 pinctrl-0 = <&qup_uart9_default>;
538 pinctrl-0 = <&qup_uart2_default>;
617 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
618 status = "disabled";
619 };
539 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
540 status = "disabled";
541 };
620
621 i2c10: i2c@990000 {
622 compatible = "qcom,geni-i2c";
623 reg = <0 0x00990000 0 0x4000>;
624 clock-names = "se";
625 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
626 pinctrl-names = "default";
627 pinctrl-0 = <&qup_i2c10_default>;
628 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
629 #address-cells = <1>;
630 #size-cells = <0>;
631 status = "disabled";
632 };
633
634 };
635
542 };
543
636 ufs_mem_hc: ufs@1d84000 {
637 compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
638 "jedec,ufs-2.0";
639 reg = <0 0x01d84000 0 0x3000>,
640 <0 0x01d90000 0 0x8000>;
641 reg-names = "std", "ice";
642 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
643 phys = <&ufs_mem_phy_lanes>;
644 phy-names = "ufsphy";
645 lanes-per-direction = <2>;
646 #reset-cells = <1>;
647 resets = <&gcc GCC_UFS_PHY_BCR>;
648 reset-names = "rst";
649
650 power-domains = <&gcc UFS_PHY_GDSC>;
651
652 iommus = <&apps_smmu 0x80 0x0>;
653
654 clock-names = "core_clk",
655 "bus_aggr_clk",
656 "iface_clk",
657 "core_clk_unipro",
658 "ref_clk",
659 "tx_lane0_sync_clk",
660 "rx_lane0_sync_clk",
661 "rx_lane1_sync_clk",
662 "ice_core_clk";
663 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
664 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
665 <&gcc GCC_UFS_PHY_AHB_CLK>,
666 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
667 <&rpmhcc RPMH_QLINK_CLK>,
668 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
669 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
670 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
671 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
672 freq-table-hz =
673 <50000000 200000000>,
674 <0 0>,
675 <0 0>,
676 <37500000 150000000>,
677 <75000000 300000000>,
678 <0 0>,
679 <0 0>,
680 <0 0>,
681 <0 0>;
682
683 status = "disabled";
684 };
685
686 ufs_mem_phy: phy@1d87000 {
687 compatible = "qcom,sm6350-qmp-ufs-phy";
688 reg = <0 0x01d87000 0 0x18c>;
689 #address-cells = <2>;
690 #size-cells = <2>;
691 ranges;
692
693 clock-names = "ref",
694 "ref_aux";
695 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
696 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
697
698 resets = <&ufs_mem_hc 0>;
699 reset-names = "ufsphy";
700
701 status = "disabled";
702
703 ufs_mem_phy_lanes: phy@1d87400 {
704 reg = <0 0x01d87400 0 0x128>,
705 <0 0x01d87600 0 0x1fc>,
706 <0 0x01d87c00 0 0x1dc>,
707 <0 0x01d87800 0 0x128>,
708 <0 0x01d87a00 0 0x1fc>;
709 #phy-cells = <0>;
710 };
711 };
712
713 tcsr_mutex: hwlock@1f40000 {
714 compatible = "qcom,tcsr-mutex";
715 reg = <0x0 0x01f40000 0x0 0x40000>;
716 #hwlock-cells = <1>;
717 };
718
719 adsp: remoteproc@3000000 {
720 compatible = "qcom,sm6350-adsp-pas";

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1029 status = "disabled";
1030 #address-cells = <2>;
1031 #size-cells = <2>;
1032 ranges;
1033
1034 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1035 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1036 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
544 tcsr_mutex: hwlock@1f40000 {
545 compatible = "qcom,tcsr-mutex";
546 reg = <0x0 0x01f40000 0x0 0x40000>;
547 #hwlock-cells = <1>;
548 };
549
550 adsp: remoteproc@3000000 {
551 compatible = "qcom,sm6350-adsp-pas";

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860 status = "disabled";
861 #address-cells = <2>;
862 #size-cells = <2>;
863 ranges;
864
865 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
866 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
867 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1037 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1038 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
1039 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1040 "sleep";
868 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
869 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
870 clock-names = "cfg_noc",
871 "core",
872 "iface",
873 "sleep",
874 "mock_utmi";
1041
1042 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1043 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
1044 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1045 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
1046
1047 interrupt-names = "hs_phy_irq", "ss_phy_irq",
1048 "dm_hs_phy_irq", "dp_hs_phy_irq";

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1138 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1139 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1140 gpio-controller;
1141 #gpio-cells = <2>;
1142 interrupt-controller;
1143 #interrupt-cells = <2>;
1144 gpio-ranges = <&tlmm 0 0 157>;
1145
875
876 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
877 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
878 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
879 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
880
881 interrupt-names = "hs_phy_irq", "ss_phy_irq",
882 "dm_hs_phy_irq", "dp_hs_phy_irq";

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972 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
974 gpio-controller;
975 #gpio-cells = <2>;
976 interrupt-controller;
977 #interrupt-cells = <2>;
978 gpio-ranges = <&tlmm 0 0 157>;
979
1146 qup_uart9_default: qup-uart9-default {
980 qup_uart2_default: qup-uart2-default {
1147 pins = "gpio25", "gpio26";
1148 function = "qup13_f2";
1149 drive-strength = <2>;
1150 bias-disable;
1151 };
981 pins = "gpio25", "gpio26";
982 function = "qup13_f2";
983 drive-strength = <2>;
984 bias-disable;
985 };
1152
1153 qup_i2c0_default: qup-i2c0-default {
1154 pins = "gpio0", "gpio1";
1155 function = "qup00";
1156 drive-strength = <2>;
1157 bias-pull-up;
1158 };
1159
1160 qup_i2c2_default: qup-i2c2-default {
1161 pins = "gpio45", "gpio46";
1162 function = "qup02";
1163 drive-strength = <2>;
1164 bias-pull-up;
1165 };
1166
1167 qup_i2c6_default: qup-i2c6-default {
1168 pins = "gpio13", "gpio14";
1169 function = "qup10";
1170 drive-strength = <2>;
1171 bias-pull-up;
1172 };
1173
1174 qup_i2c7_default: qup-i2c7-default {
1175 pins = "gpio27", "gpio28";
1176 function = "qup11";
1177 drive-strength = <2>;
1178 bias-pull-up;
1179 };
1180
1181 qup_i2c8_default: qup-i2c8-default {
1182 pins = "gpio19", "gpio20";
1183 function = "qup12";
1184 drive-strength = <2>;
1185 bias-pull-up;
1186 };
1187
1188 qup_i2c10_default: qup-i2c10-default {
1189 pins = "gpio4", "gpio5";
1190 function = "qup14";
1191 drive-strength = <2>;
1192 bias-pull-up;
1193 };
1194 };
1195
1196 apps_smmu: iommu@15000000 {
1197 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
1198 reg = <0 0x15000000 0 0x100000>;
1199 #iommu-cells = <2>;
1200 #global-interrupts = <1>;
1201 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,

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1351 frame@17c2d000 {
1352 frame-number = <6>;
1353 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1354 reg = <0x0 0x17c2d000 0x0 0x1000>;
1355 status = "disabled";
1356 };
1357 };
1358
986 };
987
988 apps_smmu: iommu@15000000 {
989 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
990 reg = <0 0x15000000 0 0x100000>;
991 #iommu-cells = <2>;
992 #global-interrupts = <1>;
993 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,

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1143 frame@17c2d000 {
1144 frame-number = <6>;
1145 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1146 reg = <0x0 0x17c2d000 0x0 0x1000>;
1147 status = "disabled";
1148 };
1149 };
1150
1359 wifi: wifi@18800000 {
1360 compatible = "qcom,wcn3990-wifi";
1361 reg = <0 0x18800000 0 0x800000>;
1362 reg-names = "membase";
1363 memory-region = <&wlan_fw_mem>;
1364 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1376 iommus = <&apps_smmu 0x20 0x1>;
1377 qcom,msa-fixed-perm;
1378 status = "disabled";
1379 };
1380
1381 apps_rsc: rsc@18200000 {
1382 compatible = "qcom,rpmh-rsc";
1383 label = "apps_rsc";
1384 reg = <0x0 0x18200000 0x0 0x10000>,
1385 <0x0 0x18210000 0x0 0x10000>,
1386 <0x0 0x18220000 0x0 0x10000>;
1387 reg-names = "drv-0", "drv-1", "drv-2";
1388 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

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1445 };
1446
1447 rpmhpd_opp_turbo_l1: opp10 {
1448 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1449 };
1450 };
1451 };
1452
1151 apps_rsc: rsc@18200000 {
1152 compatible = "qcom,rpmh-rsc";
1153 label = "apps_rsc";
1154 reg = <0x0 0x18200000 0x0 0x10000>,
1155 <0x0 0x18210000 0x0 0x10000>,
1156 <0x0 0x18220000 0x0 0x10000>;
1157 reg-names = "drv-0", "drv-1", "drv-2";
1158 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

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1215 };
1216
1217 rpmhpd_opp_turbo_l1: opp10 {
1218 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1219 };
1220 };
1221 };
1222
1453 apps_bcm_voter: bcm-voter {
1223 apps_bcm_voter: bcm_voter {
1454 compatible = "qcom,bcm-voter";
1455 };
1456 };
1457
1458 cpufreq_hw: cpufreq@18323000 {
1459 compatible = "qcom,cpufreq-hw";
1460 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
1461 reg-names = "freq-domain0", "freq-domain1";

--- 16 unchanged lines hidden --- 		1224 compatible = "qcom,bcm-voter";
1225 };
1226 };
1227
1228 cpufreq_hw: cpufreq@18323000 {
1229 compatible = "qcom,cpufreq-hw";
1230 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
1231 reg-names = "freq-domain0", "freq-domain1";

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