sc7280.dtsi (876f7a438e4247a948268ad77b67c494f709cc30) sc7280.dtsi (73419e4d2fd1b838fcb1df6a978d67b3ae1c5c01)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * sc7280 SoC device tree source
4 *
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
6 */
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * sc7280 SoC device tree source
4 *
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
6 */
7
7#include <dt-bindings/clock/qcom,camcc-sc7280.h>
8#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9#include <dt-bindings/clock/qcom,gcc-sc7280.h>
10#include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11#include <dt-bindings/clock/qcom,rpmh.h>
12#include <dt-bindings/clock/qcom,videocc-sc7280.h>
8#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9#include <dt-bindings/clock/qcom,gcc-sc7280.h>
10#include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11#include <dt-bindings/clock/qcom,rpmh.h>
12#include <dt-bindings/clock/qcom,videocc-sc7280.h>
13#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/interconnect/qcom,sc7280.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/mailbox/qcom-ipcc.h>
16#include <dt-bindings/power/qcom-rpmpd.h>
17#include <dt-bindings/reset/qcom,sdm845-aoss.h>
18#include <dt-bindings/reset/qcom,sdm845-pdc.h>
19#include <dt-bindings/soc/qcom,rpmh-rsc.h>
20#include <dt-bindings/thermal/thermal.h>

--- 1688 unchanged lines hidden (view full) ---

1709 clocks = <&rpmhcc RPMH_IPA_CLK>;
1710 clock-names = "core";
1711
1712 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1713 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
1714 interconnect-names = "memory",
1715 "config";
1716
14#include <dt-bindings/interconnect/qcom,sc7280.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/mailbox/qcom-ipcc.h>
17#include <dt-bindings/power/qcom-rpmpd.h>
18#include <dt-bindings/reset/qcom,sdm845-aoss.h>
19#include <dt-bindings/reset/qcom,sdm845-pdc.h>
20#include <dt-bindings/soc/qcom,rpmh-rsc.h>
21#include <dt-bindings/thermal/thermal.h>

--- 1688 unchanged lines hidden (view full) ---

1710 clocks = <&rpmhcc RPMH_IPA_CLK>;
1711 clock-names = "core";
1712
1713 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1714 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
1715 interconnect-names = "memory",
1716 "config";
1717
1718 qcom,qmp = <&aoss_qmp>;
1719
1717 qcom,smem-states = <&ipa_smp2p_out 0>,
1718 <&ipa_smp2p_out 1>;
1719 qcom,smem-state-names = "ipa-clock-enabled-valid",
1720 "ipa-clock-enabled";
1721
1722 status = "disabled";
1723 };
1724

--- 60 unchanged lines hidden (view full) ---

1785 opp-550000000 {
1786 opp-hz = /bits/ 64 <550000000>;
1787 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1788 opp-peak-kBps = <6832000>;
1789 };
1790 };
1791 };
1792
1720 qcom,smem-states = <&ipa_smp2p_out 0>,
1721 <&ipa_smp2p_out 1>;
1722 qcom,smem-state-names = "ipa-clock-enabled-valid",
1723 "ipa-clock-enabled";
1724
1725 status = "disabled";
1726 };
1727

--- 60 unchanged lines hidden (view full) ---

1788 opp-550000000 {
1789 opp-hz = /bits/ 64 <550000000>;
1790 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1791 opp-peak-kBps = <6832000>;
1792 };
1793 };
1794 };
1795
1793 gmu: gmu@3d69000 {
1796 gmu: gmu@3d6a000 {
1794 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
1795 reg = <0 0x03d6a000 0 0x34000>,
1796 <0 0x3de0000 0 0x10000>,
1797 <0 0x0b290000 0 0x10000>;
1798 reg-names = "gmu", "rscc", "gmu_pdc";
1799 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1800 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1801 interrupt-names = "hfi", "gmu";

--- 954 unchanged lines hidden (view full) ---

2756 clocks = <&rpmhcc RPMH_CXO_CLK>,
2757 <&rpmhcc RPMH_CXO_CLK_A>;
2758 clock-names = "bi_tcxo", "bi_tcxo_ao";
2759 #clock-cells = <1>;
2760 #reset-cells = <1>;
2761 #power-domain-cells = <1>;
2762 };
2763
1797 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
1798 reg = <0 0x03d6a000 0 0x34000>,
1799 <0 0x3de0000 0 0x10000>,
1800 <0 0x0b290000 0 0x10000>;
1801 reg-names = "gmu", "rscc", "gmu_pdc";
1802 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1803 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1804 interrupt-names = "hfi", "gmu";

--- 954 unchanged lines hidden (view full) ---

2759 clocks = <&rpmhcc RPMH_CXO_CLK>,
2760 <&rpmhcc RPMH_CXO_CLK_A>;
2761 clock-names = "bi_tcxo", "bi_tcxo_ao";
2762 #clock-cells = <1>;
2763 #reset-cells = <1>;
2764 #power-domain-cells = <1>;
2765 };
2766
2767 camcc: clock-controller@ad00000 {
2768 compatible = "qcom,sc7280-camcc";
2769 reg = <0 0x0ad00000 0 0x10000>;
2770 clocks = <&rpmhcc RPMH_CXO_CLK>,
2771 <&rpmhcc RPMH_CXO_CLK_A>,
2772 <&sleep_clk>;
2773 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
2774 #clock-cells = <1>;
2775 #reset-cells = <1>;
2776 #power-domain-cells = <1>;
2777 };
2778
2764 dispcc: clock-controller@af00000 {
2765 compatible = "qcom,sc7280-dispcc";
2766 reg = <0 0xaf00000 0 0x20000>;
2767 clocks = <&rpmhcc RPMH_CXO_CLK>,
2768 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
2779 dispcc: clock-controller@af00000 {
2780 compatible = "qcom,sc7280-dispcc";
2781 reg = <0 0xaf00000 0 0x20000>;
2782 clocks = <&rpmhcc RPMH_CXO_CLK>,
2783 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
2769 <0>, <0>, <0>, <0>, <0>, <0>;
2770 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
2784 <&mdss_dsi_phy 0>,
2785 <&mdss_dsi_phy 1>,
2786 <&dp_phy 0>,
2787 <&dp_phy 1>,
2788 <&mdss_edp_phy 0>,
2789 <&mdss_edp_phy 1>;
2790 clock-names = "bi_tcxo",
2791 "gcc_disp_gpll0_clk",
2771 "dsi0_phy_pll_out_byteclk",
2772 "dsi0_phy_pll_out_dsiclk",
2773 "dp_phy_pll_link_clk",
2774 "dp_phy_pll_vco_div_clk",
2775 "edp_phy_pll_link_clk",
2776 "edp_phy_pll_vco_div_clk";
2777 #clock-cells = <1>;
2778 #reset-cells = <1>;
2779 #power-domain-cells = <1>;
2780 };
2781
2792 "dsi0_phy_pll_out_byteclk",
2793 "dsi0_phy_pll_out_dsiclk",
2794 "dp_phy_pll_link_clk",
2795 "dp_phy_pll_vco_div_clk",
2796 "edp_phy_pll_link_clk",
2797 "edp_phy_pll_vco_div_clk";
2798 #clock-cells = <1>;
2799 #reset-cells = <1>;
2800 #power-domain-cells = <1>;
2801 };
2802
2803 mdss: display-subsystem@ae00000 {
2804 compatible = "qcom,sc7280-mdss";
2805 reg = <0 0x0ae00000 0 0x1000>;
2806 reg-names = "mdss";
2807
2808 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
2809
2810 clocks = <&gcc GCC_DISP_AHB_CLK>,
2811 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2812 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2813 clock-names = "iface",
2814 "ahb",
2815 "core";
2816
2817 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2818 assigned-clock-rates = <300000000>;
2819
2820 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2821 interrupt-controller;
2822 #interrupt-cells = <1>;
2823
2824 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
2825 interconnect-names = "mdp0-mem";
2826
2827 iommus = <&apps_smmu 0x900 0x402>;
2828
2829 #address-cells = <2>;
2830 #size-cells = <2>;
2831 ranges;
2832
2833 status = "disabled";
2834
2835 mdss_mdp: display-controller@ae01000 {
2836 compatible = "qcom,sc7280-dpu";
2837 reg = <0 0x0ae01000 0 0x8f030>,
2838 <0 0x0aeb0000 0 0x2008>;
2839 reg-names = "mdp", "vbif";
2840
2841 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2842 <&gcc GCC_DISP_SF_AXI_CLK>,
2843 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2844 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2845 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2846 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2847 clock-names = "bus",
2848 "nrt_bus",
2849 "iface",
2850 "lut",
2851 "core",
2852 "vsync";
2853 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2854 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2855 <&dispcc DISP_CC_MDSS_AHB_CLK>;
2856 assigned-clock-rates = <300000000>,
2857 <19200000>,
2858 <19200000>;
2859 operating-points-v2 = <&mdp_opp_table>;
2860 power-domains = <&rpmhpd SC7280_CX>;
2861
2862 interrupt-parent = <&mdss>;
2863 interrupts = <0>;
2864
2865 status = "disabled";
2866
2867 ports {
2868 #address-cells = <1>;
2869 #size-cells = <0>;
2870
2871 port@0 {
2872 reg = <0>;
2873 dpu_intf1_out: endpoint {
2874 remote-endpoint = <&dsi0_in>;
2875 };
2876 };
2877
2878 port@1 {
2879 reg = <1>;
2880 dpu_intf5_out: endpoint {
2881 remote-endpoint = <&edp_in>;
2882 };
2883 };
2884
2885 port@2 {
2886 reg = <2>;
2887 dpu_intf0_out: endpoint {
2888 remote-endpoint = <&dp_in>;
2889 };
2890 };
2891 };
2892
2893 mdp_opp_table: opp-table {
2894 compatible = "operating-points-v2";
2895
2896 opp-200000000 {
2897 opp-hz = /bits/ 64 <200000000>;
2898 required-opps = <&rpmhpd_opp_low_svs>;
2899 };
2900
2901 opp-300000000 {
2902 opp-hz = /bits/ 64 <300000000>;
2903 required-opps = <&rpmhpd_opp_svs>;
2904 };
2905
2906 opp-380000000 {
2907 opp-hz = /bits/ 64 <380000000>;
2908 required-opps = <&rpmhpd_opp_svs_l1>;
2909 };
2910
2911 opp-506666667 {
2912 opp-hz = /bits/ 64 <506666667>;
2913 required-opps = <&rpmhpd_opp_nom>;
2914 };
2915 };
2916 };
2917
2918 mdss_dsi: dsi@ae94000 {
2919 compatible = "qcom,mdss-dsi-ctrl";
2920 reg = <0 0x0ae94000 0 0x400>;
2921 reg-names = "dsi_ctrl";
2922
2923 interrupt-parent = <&mdss>;
2924 interrupts = <4>;
2925
2926 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2927 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2928 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2929 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2930 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2931 <&gcc GCC_DISP_HF_AXI_CLK>;
2932 clock-names = "byte",
2933 "byte_intf",
2934 "pixel",
2935 "core",
2936 "iface",
2937 "bus";
2938
2939 operating-points-v2 = <&dsi_opp_table>;
2940 power-domains = <&rpmhpd SC7280_CX>;
2941
2942 phys = <&mdss_dsi_phy>;
2943 phy-names = "dsi";
2944
2945 #address-cells = <1>;
2946 #size-cells = <0>;
2947
2948 status = "disabled";
2949
2950 ports {
2951 #address-cells = <1>;
2952 #size-cells = <0>;
2953
2954 port@0 {
2955 reg = <0>;
2956 dsi0_in: endpoint {
2957 remote-endpoint = <&dpu_intf1_out>;
2958 };
2959 };
2960
2961 port@1 {
2962 reg = <1>;
2963 dsi0_out: endpoint {
2964 };
2965 };
2966 };
2967
2968 dsi_opp_table: opp-table {
2969 compatible = "operating-points-v2";
2970
2971 opp-187500000 {
2972 opp-hz = /bits/ 64 <187500000>;
2973 required-opps = <&rpmhpd_opp_low_svs>;
2974 };
2975
2976 opp-300000000 {
2977 opp-hz = /bits/ 64 <300000000>;
2978 required-opps = <&rpmhpd_opp_svs>;
2979 };
2980
2981 opp-358000000 {
2982 opp-hz = /bits/ 64 <358000000>;
2983 required-opps = <&rpmhpd_opp_svs_l1>;
2984 };
2985 };
2986 };
2987
2988 mdss_dsi_phy: phy@ae94400 {
2989 compatible = "qcom,sc7280-dsi-phy-7nm";
2990 reg = <0 0x0ae94400 0 0x200>,
2991 <0 0x0ae94600 0 0x280>,
2992 <0 0x0ae94900 0 0x280>;
2993 reg-names = "dsi_phy",
2994 "dsi_phy_lane",
2995 "dsi_pll";
2996
2997 #clock-cells = <1>;
2998 #phy-cells = <0>;
2999
3000 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3001 <&rpmhcc RPMH_CXO_CLK>;
3002 clock-names = "iface", "ref";
3003
3004 status = "disabled";
3005 };
3006
3007 mdss_edp: edp@aea0000 {
3008 compatible = "qcom,sc7280-edp";
3009
3010 reg = <0 0xaea0000 0 0x200>,
3011 <0 0xaea0200 0 0x200>,
3012 <0 0xaea0400 0 0xc00>,
3013 <0 0xaea1000 0 0x400>;
3014
3015 interrupt-parent = <&mdss>;
3016 interrupts = <14>;
3017
3018 clocks = <&rpmhcc RPMH_CXO_CLK>,
3019 <&gcc GCC_EDP_CLKREF_EN>,
3020 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3021 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
3022 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
3023 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
3024 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
3025 clock-names = "core_xo",
3026 "core_ref",
3027 "core_iface",
3028 "core_aux",
3029 "ctrl_link",
3030 "ctrl_link_iface",
3031 "stream_pixel";
3032 #clock-cells = <1>;
3033 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
3034 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
3035 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
3036
3037 phys = <&mdss_edp_phy>;
3038 phy-names = "dp";
3039
3040 operating-points-v2 = <&edp_opp_table>;
3041 power-domains = <&rpmhpd SC7280_CX>;
3042
3043 #address-cells = <1>;
3044 #size-cells = <0>;
3045
3046 status = "disabled";
3047
3048 ports {
3049 #address-cells = <1>;
3050 #size-cells = <0>;
3051 port@0 {
3052 reg = <0>;
3053 edp_in: endpoint {
3054 remote-endpoint = <&dpu_intf5_out>;
3055 };
3056 };
3057 };
3058
3059 edp_opp_table: opp-table {
3060 compatible = "operating-points-v2";
3061
3062 opp-160000000 {
3063 opp-hz = /bits/ 64 <160000000>;
3064 required-opps = <&rpmhpd_opp_low_svs>;
3065 };
3066
3067 opp-270000000 {
3068 opp-hz = /bits/ 64 <270000000>;
3069 required-opps = <&rpmhpd_opp_svs>;
3070 };
3071
3072 opp-540000000 {
3073 opp-hz = /bits/ 64 <540000000>;
3074 required-opps = <&rpmhpd_opp_nom>;
3075 };
3076
3077 opp-810000000 {
3078 opp-hz = /bits/ 64 <810000000>;
3079 required-opps = <&rpmhpd_opp_nom>;
3080 };
3081 };
3082 };
3083
3084 mdss_edp_phy: phy@aec2a00 {
3085 compatible = "qcom,sc7280-edp-phy";
3086
3087 reg = <0 0xaec2a00 0 0x19c>,
3088 <0 0xaec2200 0 0xa0>,
3089 <0 0xaec2600 0 0xa0>,
3090 <0 0xaec2000 0 0x1c0>;
3091
3092 clocks = <&rpmhcc RPMH_CXO_CLK>,
3093 <&gcc GCC_EDP_CLKREF_EN>;
3094 clock-names = "aux",
3095 "cfg_ahb";
3096
3097 #clock-cells = <1>;
3098 #phy-cells = <0>;
3099
3100 status = "disabled";
3101 };
3102
3103 mdss_dp: displayport-controller@ae90000 {
3104 compatible = "qcom,sc7280-dp";
3105
3106 reg = <0 0x0ae90000 0 0x1400>;
3107
3108 interrupt-parent = <&mdss>;
3109 interrupts = <12>;
3110
3111 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3112 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3113 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3114 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3115 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3116 clock-names = "core_iface",
3117 "core_aux",
3118 "ctrl_link",
3119 "ctrl_link_iface",
3120 "stream_pixel";
3121 #clock-cells = <1>;
3122 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3123 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3124 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3125 phys = <&dp_phy>;
3126 phy-names = "dp";
3127
3128 operating-points-v2 = <&dp_opp_table>;
3129 power-domains = <&rpmhpd SC7280_CX>;
3130
3131 #sound-dai-cells = <0>;
3132
3133 status = "disabled";
3134
3135 ports {
3136 #address-cells = <1>;
3137 #size-cells = <0>;
3138 port@0 {
3139 reg = <0>;
3140 dp_in: endpoint {
3141 remote-endpoint = <&dpu_intf0_out>;
3142 };
3143 };
3144
3145 port@1 {
3146 reg = <1>;
3147 dp_out: endpoint { };
3148 };
3149 };
3150
3151 dp_opp_table: opp-table {
3152 compatible = "operating-points-v2";
3153
3154 opp-160000000 {
3155 opp-hz = /bits/ 64 <160000000>;
3156 required-opps = <&rpmhpd_opp_low_svs>;
3157 };
3158
3159 opp-270000000 {
3160 opp-hz = /bits/ 64 <270000000>;
3161 required-opps = <&rpmhpd_opp_svs>;
3162 };
3163
3164 opp-540000000 {
3165 opp-hz = /bits/ 64 <540000000>;
3166 required-opps = <&rpmhpd_opp_svs_l1>;
3167 };
3168
3169 opp-810000000 {
3170 opp-hz = /bits/ 64 <810000000>;
3171 required-opps = <&rpmhpd_opp_nom>;
3172 };
3173 };
3174 };
3175 };
3176
2782 pdc: interrupt-controller@b220000 {
2783 compatible = "qcom,sc7280-pdc", "qcom,pdc";
2784 reg = <0 0x0b220000 0 0x30000>;
2785 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
2786 <55 306 4>, <59 312 3>, <62 374 2>,
2787 <64 434 2>, <66 438 3>, <69 86 1>,
2788 <70 520 54>, <124 609 31>, <155 63 1>,
2789 <156 716 12>;

--- 84 unchanged lines hidden (view full) ---

2874
2875 pcie1_clkreq_n: pcie1-clkreq-n {
2876 pins = "gpio79";
2877 function = "pcie1_clkreqn";
2878 drive-strength = <2>;
2879 bias-pull-up;
2880 };
2881
3177 pdc: interrupt-controller@b220000 {
3178 compatible = "qcom,sc7280-pdc", "qcom,pdc";
3179 reg = <0 0x0b220000 0 0x30000>;
3180 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
3181 <55 306 4>, <59 312 3>, <62 374 2>,
3182 <64 434 2>, <66 438 3>, <69 86 1>,
3183 <70 520 54>, <124 609 31>, <155 63 1>,
3184 <156 716 12>;

--- 84 unchanged lines hidden (view full) ---

3269
3270 pcie1_clkreq_n: pcie1-clkreq-n {
3271 pins = "gpio79";
3272 function = "pcie1_clkreqn";
3273 drive-strength = <2>;
3274 bias-pull-up;
3275 };
3276
3277 dp_hot_plug_det: dp-hot-plug-det {
3278 pins = "gpio47";
3279 function = "dp_hot";
3280 bias-disable;
3281 };
3282
2882 qspi_clk: qspi-clk {
2883 pins = "gpio14";
2884 function = "qspi_clk";
2885 };
2886
2887 qspi_cs0: qspi-cs0 {
2888 pins = "gpio15";
2889 function = "qspi_cs";

--- 1874 unchanged lines hidden --- 		3283 qspi_clk: qspi-clk {
3284 pins = "gpio14";
3285 function = "qspi_clk";
3286 };
3287
3288 qspi_cs0: qspi-cs0 {
3289 pins = "gpio15";
3290 function = "qspi_cs";

--- 1874 unchanged lines hidden ---