sc7180.dtsi (fa8da06628626531cda3a008223d99109cbd1f02) sc7180.dtsi (0a4fd091cf11203c3f0415be85c70daf8db0bd4f)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,dispcc-sc7180.h>

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2795 mdss: mdss@ae00000 {
2796 compatible = "qcom,sc7180-mdss";
2797 reg = <0 0x0ae00000 0 0x1000>;
2798 reg-names = "mdss";
2799
2800 power-domains = <&dispcc MDSS_GDSC>;
2801
2802 clocks = <&gcc GCC_DISP_AHB_CLK>,
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,dispcc-sc7180.h>

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2795 mdss: mdss@ae00000 {
2796 compatible = "qcom,sc7180-mdss";
2797 reg = <0 0x0ae00000 0 0x1000>;
2798 reg-names = "mdss";
2799
2800 power-domains = <&dispcc MDSS_GDSC>;
2801
2802 clocks = <&gcc GCC_DISP_AHB_CLK>,
2803 <&gcc GCC_DISP_HF_AXI_CLK>,
2804 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2805 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2803 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2804 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2806 clock-names = "iface", "bus", "ahb", "core";
2805 clock-names = "iface", "ahb", "core";
2807
2808 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2809 assigned-clock-rates = <300000000>;
2810
2811 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2812 interrupt-controller;
2813 #interrupt-cells = <1>;
2814

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2824 status = "disabled";
2825
2826 mdp: mdp@ae01000 {
2827 compatible = "qcom,sc7180-dpu";
2828 reg = <0 0x0ae01000 0 0x8f000>,
2829 <0 0x0aeb0000 0 0x2008>;
2830 reg-names = "mdp", "vbif";
2831
2806
2807 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2808 assigned-clock-rates = <300000000>;
2809
2810 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2811 interrupt-controller;
2812 #interrupt-cells = <1>;
2813

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2823 status = "disabled";
2824
2825 mdp: mdp@ae01000 {
2826 compatible = "qcom,sc7180-dpu";
2827 reg = <0 0x0ae01000 0 0x8f000>,
2828 <0 0x0aeb0000 0 0x2008>;
2829 reg-names = "mdp", "vbif";
2830
2832 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2831 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2832 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2833 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2834 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2835 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2836 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2833 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2834 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2835 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2836 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2837 clock-names = "iface", "rot", "lut", "core",
2837 clock-names = "bus", "iface", "rot", "lut", "core",
2838 "vsync";
2839 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2840 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2841 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2842 <&dispcc DISP_CC_MDSS_AHB_CLK>;
2843 assigned-clock-rates = <300000000>,
2844 <19200000>,
2845 <19200000>,

--- 1338 unchanged lines hidden --- 		2838 "vsync";
2839 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2840 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2841 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2842 <&dispcc DISP_CC_MDSS_AHB_CLK>;
2843 assigned-clock-rates = <300000000>,
2844 <19200000>,
2845 <19200000>,

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