sc7180.dtsi (e700ac213a0f793fb4f83098413303e3dd080892) sc7180.dtsi (dfe28877db61e82ba3b57b50d73096ef11563d72)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9#include <dt-bindings/clock/qcom,gcc-sc7180.h>
10#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12#include <dt-bindings/clock/qcom,rpmh.h>
13#include <dt-bindings/clock/qcom,videocc-sc7180.h>
14#include <dt-bindings/interconnect/qcom,osm-l3.h>
15#include <dt-bindings/interconnect/qcom,sc7180.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/phy/phy-qcom-qusb2.h>
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9#include <dt-bindings/clock/qcom,gcc-sc7180.h>
10#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12#include <dt-bindings/clock/qcom,rpmh.h>
13#include <dt-bindings/clock/qcom,videocc-sc7180.h>
14#include <dt-bindings/interconnect/qcom,osm-l3.h>
15#include <dt-bindings/interconnect/qcom,sc7180.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/phy/phy-qcom-qusb2.h>
18#include <dt-bindings/power/qcom-aoss-qmp.h>
19#include <dt-bindings/power/qcom-rpmpd.h>
20#include <dt-bindings/reset/qcom,sdm845-aoss.h>
21#include <dt-bindings/reset/qcom,sdm845-pdc.h>
22#include <dt-bindings/soc/qcom,rpmh-rsc.h>
23#include <dt-bindings/thermal/thermal.h>
24
25/ {
26 interrupt-parent = <&intc>;

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132 CPU0: cpu@0 {
133 device_type = "cpu";
134 compatible = "qcom,kryo468";
135 reg = <0x0 0x0>;
136 enable-method = "psci";
137 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
138 &LITTLE_CPU_SLEEP_1
139 &CLUSTER_SLEEP_0>;
18#include <dt-bindings/power/qcom-rpmpd.h>
19#include <dt-bindings/reset/qcom,sdm845-aoss.h>
20#include <dt-bindings/reset/qcom,sdm845-pdc.h>
21#include <dt-bindings/soc/qcom,rpmh-rsc.h>
22#include <dt-bindings/thermal/thermal.h>
23
24/ {
25 interrupt-parent = <&intc>;

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131 CPU0: cpu@0 {
132 device_type = "cpu";
133 compatible = "qcom,kryo468";
134 reg = <0x0 0x0>;
135 enable-method = "psci";
136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
137 &LITTLE_CPU_SLEEP_1
138 &CLUSTER_SLEEP_0>;
140 capacity-dmips-mhz = <1024>;
141 dynamic-power-coefficient = <100>;
139 capacity-dmips-mhz = <415>;
140 dynamic-power-coefficient = <137>;
142 operating-points-v2 = <&cpu0_opp_table>;
143 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
144 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
145 next-level-cache = <&L2_0>;
146 #cooling-cells = <2>;
147 qcom,freq-domain = <&cpufreq_hw 0>;
148 L2_0: l2-cache {
149 compatible = "cache";

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157 CPU1: cpu@100 {
158 device_type = "cpu";
159 compatible = "qcom,kryo468";
160 reg = <0x0 0x100>;
161 enable-method = "psci";
162 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
163 &LITTLE_CPU_SLEEP_1
164 &CLUSTER_SLEEP_0>;
141 operating-points-v2 = <&cpu0_opp_table>;
142 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
143 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
144 next-level-cache = <&L2_0>;
145 #cooling-cells = <2>;
146 qcom,freq-domain = <&cpufreq_hw 0>;
147 L2_0: l2-cache {
148 compatible = "cache";

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156 CPU1: cpu@100 {
157 device_type = "cpu";
158 compatible = "qcom,kryo468";
159 reg = <0x0 0x100>;
160 enable-method = "psci";
161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
162 &LITTLE_CPU_SLEEP_1
163 &CLUSTER_SLEEP_0>;
165 capacity-dmips-mhz = <1024>;
166 dynamic-power-coefficient = <100>;
164 capacity-dmips-mhz = <415>;
165 dynamic-power-coefficient = <137>;
167 next-level-cache = <&L2_100>;
168 operating-points-v2 = <&cpu0_opp_table>;
169 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
170 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
171 #cooling-cells = <2>;
172 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_100: l2-cache {
174 compatible = "cache";

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179 CPU2: cpu@200 {
180 device_type = "cpu";
181 compatible = "qcom,kryo468";
182 reg = <0x0 0x200>;
183 enable-method = "psci";
184 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
185 &LITTLE_CPU_SLEEP_1
186 &CLUSTER_SLEEP_0>;
166 next-level-cache = <&L2_100>;
167 operating-points-v2 = <&cpu0_opp_table>;
168 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
170 #cooling-cells = <2>;
171 qcom,freq-domain = <&cpufreq_hw 0>;
172 L2_100: l2-cache {
173 compatible = "cache";

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178 CPU2: cpu@200 {
179 device_type = "cpu";
180 compatible = "qcom,kryo468";
181 reg = <0x0 0x200>;
182 enable-method = "psci";
183 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
184 &LITTLE_CPU_SLEEP_1
185 &CLUSTER_SLEEP_0>;
187 capacity-dmips-mhz = <1024>;
188 dynamic-power-coefficient = <100>;
186 capacity-dmips-mhz = <415>;
187 dynamic-power-coefficient = <137>;
189 next-level-cache = <&L2_200>;
190 operating-points-v2 = <&cpu0_opp_table>;
191 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
192 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
193 #cooling-cells = <2>;
194 qcom,freq-domain = <&cpufreq_hw 0>;
195 L2_200: l2-cache {
196 compatible = "cache";

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201 CPU3: cpu@300 {
202 device_type = "cpu";
203 compatible = "qcom,kryo468";
204 reg = <0x0 0x300>;
205 enable-method = "psci";
206 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
207 &LITTLE_CPU_SLEEP_1
208 &CLUSTER_SLEEP_0>;
188 next-level-cache = <&L2_200>;
189 operating-points-v2 = <&cpu0_opp_table>;
190 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
191 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
192 #cooling-cells = <2>;
193 qcom,freq-domain = <&cpufreq_hw 0>;
194 L2_200: l2-cache {
195 compatible = "cache";

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200 CPU3: cpu@300 {
201 device_type = "cpu";
202 compatible = "qcom,kryo468";
203 reg = <0x0 0x300>;
204 enable-method = "psci";
205 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
206 &LITTLE_CPU_SLEEP_1
207 &CLUSTER_SLEEP_0>;
209 capacity-dmips-mhz = <1024>;
210 dynamic-power-coefficient = <100>;
208 capacity-dmips-mhz = <415>;
209 dynamic-power-coefficient = <137>;
211 next-level-cache = <&L2_300>;
212 operating-points-v2 = <&cpu0_opp_table>;
213 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
214 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
215 #cooling-cells = <2>;
216 qcom,freq-domain = <&cpufreq_hw 0>;
217 L2_300: l2-cache {
218 compatible = "cache";

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223 CPU4: cpu@400 {
224 device_type = "cpu";
225 compatible = "qcom,kryo468";
226 reg = <0x0 0x400>;
227 enable-method = "psci";
228 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
229 &LITTLE_CPU_SLEEP_1
230 &CLUSTER_SLEEP_0>;
210 next-level-cache = <&L2_300>;
211 operating-points-v2 = <&cpu0_opp_table>;
212 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
213 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
214 #cooling-cells = <2>;
215 qcom,freq-domain = <&cpufreq_hw 0>;
216 L2_300: l2-cache {
217 compatible = "cache";

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222 CPU4: cpu@400 {
223 device_type = "cpu";
224 compatible = "qcom,kryo468";
225 reg = <0x0 0x400>;
226 enable-method = "psci";
227 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
228 &LITTLE_CPU_SLEEP_1
229 &CLUSTER_SLEEP_0>;
231 capacity-dmips-mhz = <1024>;
232 dynamic-power-coefficient = <100>;
230 capacity-dmips-mhz = <415>;
231 dynamic-power-coefficient = <137>;
233 next-level-cache = <&L2_400>;
234 operating-points-v2 = <&cpu0_opp_table>;
235 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
236 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
237 #cooling-cells = <2>;
238 qcom,freq-domain = <&cpufreq_hw 0>;
239 L2_400: l2-cache {
240 compatible = "cache";

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245 CPU5: cpu@500 {
246 device_type = "cpu";
247 compatible = "qcom,kryo468";
248 reg = <0x0 0x500>;
249 enable-method = "psci";
250 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
251 &LITTLE_CPU_SLEEP_1
252 &CLUSTER_SLEEP_0>;
232 next-level-cache = <&L2_400>;
233 operating-points-v2 = <&cpu0_opp_table>;
234 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
235 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
236 #cooling-cells = <2>;
237 qcom,freq-domain = <&cpufreq_hw 0>;
238 L2_400: l2-cache {
239 compatible = "cache";

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244 CPU5: cpu@500 {
245 device_type = "cpu";
246 compatible = "qcom,kryo468";
247 reg = <0x0 0x500>;
248 enable-method = "psci";
249 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
250 &LITTLE_CPU_SLEEP_1
251 &CLUSTER_SLEEP_0>;
253 capacity-dmips-mhz = <1024>;
254 dynamic-power-coefficient = <100>;
252 capacity-dmips-mhz = <415>;
253 dynamic-power-coefficient = <137>;
255 next-level-cache = <&L2_500>;
256 operating-points-v2 = <&cpu0_opp_table>;
257 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
258 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
259 #cooling-cells = <2>;
260 qcom,freq-domain = <&cpufreq_hw 0>;
261 L2_500: l2-cache {
262 compatible = "cache";

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267 CPU6: cpu@600 {
268 device_type = "cpu";
269 compatible = "qcom,kryo468";
270 reg = <0x0 0x600>;
271 enable-method = "psci";
272 cpu-idle-states = <&BIG_CPU_SLEEP_0
273 &BIG_CPU_SLEEP_1
274 &CLUSTER_SLEEP_0>;
254 next-level-cache = <&L2_500>;
255 operating-points-v2 = <&cpu0_opp_table>;
256 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
257 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
258 #cooling-cells = <2>;
259 qcom,freq-domain = <&cpufreq_hw 0>;
260 L2_500: l2-cache {
261 compatible = "cache";

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266 CPU6: cpu@600 {
267 device_type = "cpu";
268 compatible = "qcom,kryo468";
269 reg = <0x0 0x600>;
270 enable-method = "psci";
271 cpu-idle-states = <&BIG_CPU_SLEEP_0
272 &BIG_CPU_SLEEP_1
273 &CLUSTER_SLEEP_0>;
275 capacity-dmips-mhz = <1740>;
276 dynamic-power-coefficient = <405>;
274 capacity-dmips-mhz = <1024>;
275 dynamic-power-coefficient = <480>;
277 next-level-cache = <&L2_600>;
278 operating-points-v2 = <&cpu6_opp_table>;
279 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
280 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
281 #cooling-cells = <2>;
282 qcom,freq-domain = <&cpufreq_hw 1>;
283 L2_600: l2-cache {
284 compatible = "cache";

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289 CPU7: cpu@700 {
290 device_type = "cpu";
291 compatible = "qcom,kryo468";
292 reg = <0x0 0x700>;
293 enable-method = "psci";
294 cpu-idle-states = <&BIG_CPU_SLEEP_0
295 &BIG_CPU_SLEEP_1
296 &CLUSTER_SLEEP_0>;
276 next-level-cache = <&L2_600>;
277 operating-points-v2 = <&cpu6_opp_table>;
278 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
279 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
280 #cooling-cells = <2>;
281 qcom,freq-domain = <&cpufreq_hw 1>;
282 L2_600: l2-cache {
283 compatible = "cache";

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288 CPU7: cpu@700 {
289 device_type = "cpu";
290 compatible = "qcom,kryo468";
291 reg = <0x0 0x700>;
292 enable-method = "psci";
293 cpu-idle-states = <&BIG_CPU_SLEEP_0
294 &BIG_CPU_SLEEP_1
295 &CLUSTER_SLEEP_0>;
297 capacity-dmips-mhz = <1740>;
298 dynamic-power-coefficient = <405>;
296 capacity-dmips-mhz = <1024>;
297 dynamic-power-coefficient = <480>;
299 next-level-cache = <&L2_700>;
300 operating-points-v2 = <&cpu6_opp_table>;
301 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
302 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
303 #cooling-cells = <2>;
304 qcom,freq-domain = <&cpufreq_hw 1>;
305 L2_700: l2-cache {
306 compatible = "cache";

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1917 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
1918 <&gcc GCC_MSS_NAV_AXI_CLK>,
1919 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1920 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
1921 <&rpmhcc RPMH_CXO_CLK>;
1922 clock-names = "iface", "bus", "nav", "snoc_axi",
1923 "mnoc_axi", "xo";
1924
298 next-level-cache = <&L2_700>;
299 operating-points-v2 = <&cpu6_opp_table>;
300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
301 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
302 #cooling-cells = <2>;
303 qcom,freq-domain = <&cpufreq_hw 1>;
304 L2_700: l2-cache {
305 compatible = "cache";

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1916 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
1917 <&gcc GCC_MSS_NAV_AXI_CLK>,
1918 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1919 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
1920 <&rpmhcc RPMH_CXO_CLK>;
1921 clock-names = "iface", "bus", "nav", "snoc_axi",
1922 "mnoc_axi", "xo";
1923
1925 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
1926 <&rpmhpd SC7180_CX>,
1924 power-domains = <&rpmhpd SC7180_CX>,
1927 <&rpmhpd SC7180_MX>,
1928 <&rpmhpd SC7180_MSS>;
1925 <&rpmhpd SC7180_MX>,
1926 <&rpmhpd SC7180_MSS>;
1929 power-domain-names = "load_state", "cx", "mx", "mss";
1927 power-domain-names = "cx", "mx", "mss";
1930
1931 memory-region = <&mpss_mem>;
1932
1928
1929 memory-region = <&mpss_mem>;
1930
1931 qcom,qmp = <&aoss_qmp>;
1932
1933 qcom,smem-states = <&modem_smp2p_out 0>;
1934 qcom,smem-state-names = "stop";
1935
1936 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
1937 <&pdc_reset PDC_MODEM_SYNC_RESET>;
1938 reset-names = "mss_restart", "pdc_reset";
1939
1940 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;

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2642
2643 opp-300000000 {
2644 opp-hz = /bits/ 64 <300000000>;
2645 required-opps = <&rpmhpd_opp_nom>;
2646 };
2647 };
2648
2649 qspi: spi@88dc000 {
1933 qcom,smem-states = <&modem_smp2p_out 0>;
1934 qcom,smem-state-names = "stop";
1935
1936 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
1937 <&pdc_reset PDC_MODEM_SYNC_RESET>;
1938 reset-names = "mss_restart", "pdc_reset";
1939
1940 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;

--- 701 unchanged lines hidden (view full) ---

2642
2643 opp-300000000 {
2644 opp-hz = /bits/ 64 <300000000>;
2645 required-opps = <&rpmhpd_opp_nom>;
2646 };
2647 };
2648
2649 qspi: spi@88dc000 {
2650 compatible = "qcom,qspi-v1";
2650 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2651 reg = <0 0x088dc000 0 0x600>;
2652 #address-cells = <1>;
2653 #size-cells = <0>;
2654 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2655 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2656 <&gcc GCC_QSPI_CORE_CLK>;
2657 clock-names = "iface", "core";
2658 interconnects = <&gem_noc MASTER_APPSS_PROC 0

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3219
3220 aoss_qmp: power-controller@c300000 {
3221 compatible = "qcom,sc7180-aoss-qmp";
3222 reg = <0 0x0c300000 0 0x100000>;
3223 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3224 mboxes = <&apss_shared 0>;
3225
3226 #clock-cells = <0>;
2651 reg = <0 0x088dc000 0 0x600>;
2652 #address-cells = <1>;
2653 #size-cells = <0>;
2654 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2655 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2656 <&gcc GCC_QSPI_CORE_CLK>;
2657 clock-names = "iface", "core";
2658 interconnects = <&gem_noc MASTER_APPSS_PROC 0

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3219
3220 aoss_qmp: power-controller@c300000 {
3221 compatible = "qcom,sc7180-aoss-qmp";
3222 reg = <0 0x0c300000 0 0x100000>;
3223 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3224 mboxes = <&apss_shared 0>;
3225
3226 #clock-cells = <0>;
3227 #power-domain-cells = <1>;
3228 };
3229
3230 spmi_bus: spmi@c440000 {
3231 compatible = "qcom,spmi-pmic-arb";
3232 reg = <0 0x0c440000 0 0x1100>,
3233 <0 0x0c600000 0 0x2000000>,
3234 <0 0x0e600000 0 0x100000>,
3235 <0 0x0e700000 0 0xa0000>,

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3241 qcom,channel = <0>;
3242 #address-cells = <1>;
3243 #size-cells = <1>;
3244 interrupt-controller;
3245 #interrupt-cells = <4>;
3246 cell-index = <0>;
3247 };
3248
3227 };
3228
3229 spmi_bus: spmi@c440000 {
3230 compatible = "qcom,spmi-pmic-arb";
3231 reg = <0 0x0c440000 0 0x1100>,
3232 <0 0x0c600000 0 0x2000000>,
3233 <0 0x0e600000 0 0x100000>,
3234 <0 0x0e700000 0 0xa0000>,

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3240 qcom,channel = <0>;
3241 #address-cells = <1>;
3242 #size-cells = <1>;
3243 interrupt-controller;
3244 #interrupt-cells = <4>;
3245 cell-index = <0>;
3246 };
3247
3248 imem@146aa000 {
3249 compatible = "simple-mfd";
3250 reg = <0 0x146aa000 0 0x2000>;
3251
3252 #address-cells = <1>;
3253 #size-cells = <1>;
3254
3255 ranges = <0 0 0x146aa000 0x2000>;
3256
3257 pil-reloc@94c {
3258 compatible = "qcom,pil-reloc-info";
3259 reg = <0x94c 0xc8>;
3260 };
3261 };
3262
3249 apps_smmu: iommu@15000000 {
3250 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3251 reg = <0 0x15000000 0 0x100000>;
3252 #iommu-cells = <2>;
3253 #global-interrupts = <1>;
3254 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3255 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3256 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

--- 354 unchanged lines hidden (view full) ---

3611 };
3612
3613 thermal-zones {
3614 cpu0_thermal: cpu0-thermal {
3615 polling-delay-passive = <250>;
3616 polling-delay = <0>;
3617
3618 thermal-sensors = <&tsens0 1>;
3263 apps_smmu: iommu@15000000 {
3264 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3265 reg = <0 0x15000000 0 0x100000>;
3266 #iommu-cells = <2>;
3267 #global-interrupts = <1>;
3268 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3269 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3270 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

--- 354 unchanged lines hidden (view full) ---

3625 };
3626
3627 thermal-zones {
3628 cpu0_thermal: cpu0-thermal {
3629 polling-delay-passive = <250>;
3630 polling-delay = <0>;
3631
3632 thermal-sensors = <&tsens0 1>;
3619 sustainable-power = <768>;
3633 sustainable-power = <1052>;
3620
3621 trips {
3622 cpu0_alert0: trip-point0 {
3623 temperature = <90000>;
3624 hysteresis = <2000>;
3625 type = "passive";
3626 };
3627

--- 32 unchanged lines hidden (view full) ---

3660 };
3661 };
3662
3663 cpu1_thermal: cpu1-thermal {
3664 polling-delay-passive = <250>;
3665 polling-delay = <0>;
3666
3667 thermal-sensors = <&tsens0 2>;
3634
3635 trips {
3636 cpu0_alert0: trip-point0 {
3637 temperature = <90000>;
3638 hysteresis = <2000>;
3639 type = "passive";
3640 };
3641

--- 32 unchanged lines hidden (view full) ---

3674 };
3675 };
3676
3677 cpu1_thermal: cpu1-thermal {
3678 polling-delay-passive = <250>;
3679 polling-delay = <0>;
3680
3681 thermal-sensors = <&tsens0 2>;
3668 sustainable-power = <768>;
3682 sustainable-power = <1052>;
3669
3670 trips {
3671 cpu1_alert0: trip-point0 {
3672 temperature = <90000>;
3673 hysteresis = <2000>;
3674 type = "passive";
3675 };
3676

--- 32 unchanged lines hidden (view full) ---

3709 };
3710 };
3711
3712 cpu2_thermal: cpu2-thermal {
3713 polling-delay-passive = <250>;
3714 polling-delay = <0>;
3715
3716 thermal-sensors = <&tsens0 3>;
3683
3684 trips {
3685 cpu1_alert0: trip-point0 {
3686 temperature = <90000>;
3687 hysteresis = <2000>;
3688 type = "passive";
3689 };
3690

--- 32 unchanged lines hidden (view full) ---

3723 };
3724 };
3725
3726 cpu2_thermal: cpu2-thermal {
3727 polling-delay-passive = <250>;
3728 polling-delay = <0>;
3729
3730 thermal-sensors = <&tsens0 3>;
3717 sustainable-power = <768>;
3731 sustainable-power = <1052>;
3718
3719 trips {
3720 cpu2_alert0: trip-point0 {
3721 temperature = <90000>;
3722 hysteresis = <2000>;
3723 type = "passive";
3724 };
3725

--- 32 unchanged lines hidden (view full) ---

3758 };
3759 };
3760
3761 cpu3_thermal: cpu3-thermal {
3762 polling-delay-passive = <250>;
3763 polling-delay = <0>;
3764
3765 thermal-sensors = <&tsens0 4>;
3732
3733 trips {
3734 cpu2_alert0: trip-point0 {
3735 temperature = <90000>;
3736 hysteresis = <2000>;
3737 type = "passive";
3738 };
3739

--- 32 unchanged lines hidden (view full) ---

3772 };
3773 };
3774
3775 cpu3_thermal: cpu3-thermal {
3776 polling-delay-passive = <250>;
3777 polling-delay = <0>;
3778
3779 thermal-sensors = <&tsens0 4>;
3766 sustainable-power = <768>;
3780 sustainable-power = <1052>;
3767
3768 trips {
3769 cpu3_alert0: trip-point0 {
3770 temperature = <90000>;
3771 hysteresis = <2000>;
3772 type = "passive";
3773 };
3774

--- 32 unchanged lines hidden (view full) ---

3807 };
3808 };
3809
3810 cpu4_thermal: cpu4-thermal {
3811 polling-delay-passive = <250>;
3812 polling-delay = <0>;
3813
3814 thermal-sensors = <&tsens0 5>;
3781
3782 trips {
3783 cpu3_alert0: trip-point0 {
3784 temperature = <90000>;
3785 hysteresis = <2000>;
3786 type = "passive";
3787 };
3788

--- 32 unchanged lines hidden (view full) ---

3821 };
3822 };
3823
3824 cpu4_thermal: cpu4-thermal {
3825 polling-delay-passive = <250>;
3826 polling-delay = <0>;
3827
3828 thermal-sensors = <&tsens0 5>;
3815 sustainable-power = <768>;
3829 sustainable-power = <1052>;
3816
3817 trips {
3818 cpu4_alert0: trip-point0 {
3819 temperature = <90000>;
3820 hysteresis = <2000>;
3821 type = "passive";
3822 };
3823

--- 32 unchanged lines hidden (view full) ---

3856 };
3857 };
3858
3859 cpu5_thermal: cpu5-thermal {
3860 polling-delay-passive = <250>;
3861 polling-delay = <0>;
3862
3863 thermal-sensors = <&tsens0 6>;
3830
3831 trips {
3832 cpu4_alert0: trip-point0 {
3833 temperature = <90000>;
3834 hysteresis = <2000>;
3835 type = "passive";
3836 };
3837

--- 32 unchanged lines hidden (view full) ---

3870 };
3871 };
3872
3873 cpu5_thermal: cpu5-thermal {
3874 polling-delay-passive = <250>;
3875 polling-delay = <0>;
3876
3877 thermal-sensors = <&tsens0 6>;
3864 sustainable-power = <768>;
3878 sustainable-power = <1052>;
3865
3866 trips {
3867 cpu5_alert0: trip-point0 {
3868 temperature = <90000>;
3869 hysteresis = <2000>;
3870 type = "passive";
3871 };
3872

--- 32 unchanged lines hidden (view full) ---

3905 };
3906 };
3907
3908 cpu6_thermal: cpu6-thermal {
3909 polling-delay-passive = <250>;
3910 polling-delay = <0>;
3911
3912 thermal-sensors = <&tsens0 9>;
3879
3880 trips {
3881 cpu5_alert0: trip-point0 {
3882 temperature = <90000>;
3883 hysteresis = <2000>;
3884 type = "passive";
3885 };
3886

--- 32 unchanged lines hidden (view full) ---

3919 };
3920 };
3921
3922 cpu6_thermal: cpu6-thermal {
3923 polling-delay-passive = <250>;
3924 polling-delay = <0>;
3925
3926 thermal-sensors = <&tsens0 9>;
3913 sustainable-power = <1202>;
3927 sustainable-power = <1425>;
3914
3915 trips {
3916 cpu6_alert0: trip-point0 {
3917 temperature = <90000>;
3918 hysteresis = <2000>;
3919 type = "passive";
3920 };
3921

--- 24 unchanged lines hidden (view full) ---

3946 };
3947 };
3948
3949 cpu7_thermal: cpu7-thermal {
3950 polling-delay-passive = <250>;
3951 polling-delay = <0>;
3952
3953 thermal-sensors = <&tsens0 10>;
3928
3929 trips {
3930 cpu6_alert0: trip-point0 {
3931 temperature = <90000>;
3932 hysteresis = <2000>;
3933 type = "passive";
3934 };
3935

--- 24 unchanged lines hidden (view full) ---

3960 };
3961 };
3962
3963 cpu7_thermal: cpu7-thermal {
3964 polling-delay-passive = <250>;
3965 polling-delay = <0>;
3966
3967 thermal-sensors = <&tsens0 10>;
3954 sustainable-power = <1202>;
3968 sustainable-power = <1425>;
3955
3956 trips {
3957 cpu7_alert0: trip-point0 {
3958 temperature = <90000>;
3959 hysteresis = <2000>;
3960 type = "passive";
3961 };
3962

--- 24 unchanged lines hidden (view full) ---

3987 };
3988 };
3989
3990 cpu8_thermal: cpu8-thermal {
3991 polling-delay-passive = <250>;
3992 polling-delay = <0>;
3993
3994 thermal-sensors = <&tsens0 11>;
3969
3970 trips {
3971 cpu7_alert0: trip-point0 {
3972 temperature = <90000>;
3973 hysteresis = <2000>;
3974 type = "passive";
3975 };
3976

--- 24 unchanged lines hidden (view full) ---

4001 };
4002 };
4003
4004 cpu8_thermal: cpu8-thermal {
4005 polling-delay-passive = <250>;
4006 polling-delay = <0>;
4007
4008 thermal-sensors = <&tsens0 11>;
3995 sustainable-power = <1202>;
4009 sustainable-power = <1425>;
3996
3997 trips {
3998 cpu8_alert0: trip-point0 {
3999 temperature = <90000>;
4000 hysteresis = <2000>;
4001 type = "passive";
4002 };
4003

--- 24 unchanged lines hidden (view full) ---

4028 };
4029 };
4030
4031 cpu9_thermal: cpu9-thermal {
4032 polling-delay-passive = <250>;
4033 polling-delay = <0>;
4034
4035 thermal-sensors = <&tsens0 12>;
4010
4011 trips {
4012 cpu8_alert0: trip-point0 {
4013 temperature = <90000>;
4014 hysteresis = <2000>;
4015 type = "passive";
4016 };
4017

--- 24 unchanged lines hidden (view full) ---

4042 };
4043 };
4044
4045 cpu9_thermal: cpu9-thermal {
4046 polling-delay-passive = <250>;
4047 polling-delay = <0>;
4048
4049 thermal-sensors = <&tsens0 12>;
4036 sustainable-power = <1202>;
4050 sustainable-power = <1425>;
4037
4038 trips {
4039 cpu9_alert0: trip-point0 {
4040 temperature = <90000>;
4041 hysteresis = <2000>;
4042 type = "passive";
4043 };
4044

--- 363 unchanged lines hidden --- 		4051
4052 trips {
4053 cpu9_alert0: trip-point0 {
4054 temperature = <90000>;
4055 hysteresis = <2000>;
4056 type = "passive";
4057 };
4058

--- 363 unchanged lines hidden ---