sc7180.dtsi (9c3a0f285248899dfa81585bc5d5bc9ebdb8fead) sc7180.dtsi (437cdef515e29427df9c0d7e5b44b04dd17c3ff8)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,dispcc-sc7180.h>

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663 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
664 #clock-cells = <1>;
665 #reset-cells = <1>;
666 #power-domain-cells = <1>;
667 };
668
669 qfprom: efuse@784000 {
670 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,dispcc-sc7180.h>

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663 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
664 #clock-cells = <1>;
665 #reset-cells = <1>;
666 #power-domain-cells = <1>;
667 };
668
669 qfprom: efuse@784000 {
670 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
671 reg = <0 0x00784000 0 0x8ff>,
671 reg = <0 0x00784000 0 0x7a0>,
672 <0 0x00780000 0 0x7a0>,
673 <0 0x00782000 0 0x100>,
674 <0 0x00786000 0 0x1fff>;
675
676 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
677 clock-names = "core";
678 #address-cells = <1>;
679 #size-cells = <1>;

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2751 power-domains = <&gcc USB30_PRIM_GDSC>;
2752
2753 resets = <&gcc GCC_USB30_PRIM_BCR>;
2754
2755 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2756 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2757 interconnect-names = "usb-ddr", "apps-usb";
2758
672 <0 0x00780000 0 0x7a0>,
673 <0 0x00782000 0 0x100>,
674 <0 0x00786000 0 0x1fff>;
675
676 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
677 clock-names = "core";
678 #address-cells = <1>;
679 #size-cells = <1>;

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2751 power-domains = <&gcc USB30_PRIM_GDSC>;
2752
2753 resets = <&gcc GCC_USB30_PRIM_BCR>;
2754
2755 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2756 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2757 interconnect-names = "usb-ddr", "apps-usb";
2758
2759 usb_1_dwc3: dwc3@a600000 {
2759 usb_1_dwc3: usb@a600000 {
2760 compatible = "snps,dwc3";
2761 reg = <0 0x0a600000 0 0xe000>;
2762 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2763 iommus = <&apps_smmu 0x540 0>;
2764 snps,dis_u2_susphy_quirk;
2765 snps,dis_enblslpm_quirk;
2766 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2767 phy-names = "usb2-phy", "usb3-phy";

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2923 #size-cells = <0>;
2924
2925 port@0 {
2926 reg = <0>;
2927 dpu_intf1_out: endpoint {
2928 remote-endpoint = <&dsi0_in>;
2929 };
2930 };
2760 compatible = "snps,dwc3";
2761 reg = <0 0x0a600000 0 0xe000>;
2762 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2763 iommus = <&apps_smmu 0x540 0>;
2764 snps,dis_u2_susphy_quirk;
2765 snps,dis_enblslpm_quirk;
2766 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2767 phy-names = "usb2-phy", "usb3-phy";

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2923 #size-cells = <0>;
2924
2925 port@0 {
2926 reg = <0>;
2927 dpu_intf1_out: endpoint {
2928 remote-endpoint = <&dsi0_in>;
2929 };
2930 };
2931
2932 port@2 {
2933 reg = <2>;
2934 dpu_intf0_out: endpoint {
2935 remote-endpoint = <&dp_in>;
2936 };
2937 };
2931 };
2932
2933 mdp_opp_table: mdp-opp-table {
2934 compatible = "operating-points-v2";
2935
2936 opp-200000000 {
2937 opp-hz = /bits/ 64 <200000000>;
2938 required-opps = <&rpmhpd_opp_low_svs>;

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3039 #phy-cells = <0>;
3040
3041 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3042 <&rpmhcc RPMH_CXO_CLK>;
3043 clock-names = "iface", "ref";
3044
3045 status = "disabled";
3046 };
2938 };
2939
2940 mdp_opp_table: mdp-opp-table {
2941 compatible = "operating-points-v2";
2942
2943 opp-200000000 {
2944 opp-hz = /bits/ 64 <200000000>;
2945 required-opps = <&rpmhpd_opp_low_svs>;

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3046 #phy-cells = <0>;
3047
3048 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3049 <&rpmhcc RPMH_CXO_CLK>;
3050 clock-names = "iface", "ref";
3051
3052 status = "disabled";
3053 };
3054
3055 mdss_dp: displayport-controller@ae90000 {
3056 compatible = "qcom,sc7180-dp";
3057 status = "disabled";
3058
3059 reg = <0 0x0ae90000 0 0x1400>;
3060
3061 interrupt-parent = <&mdss>;
3062 interrupts = <12>;
3063
3064 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3065 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3066 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3067 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3068 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3069 clock-names = "core_iface", "core_aux", "ctrl_link",
3070 "ctrl_link_iface", "stream_pixel";
3071 #clock-cells = <1>;
3072 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3073 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3074 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3075 phys = <&dp_phy>;
3076 phy-names = "dp";
3077
3078 operating-points-v2 = <&dp_opp_table>;
3079 power-domains = <&rpmhpd SC7180_CX>;
3080
3081 #sound-dai-cells = <0>;
3082
3083 ports {
3084 #address-cells = <1>;
3085 #size-cells = <0>;
3086 port@0 {
3087 reg = <0>;
3088 dp_in: endpoint {
3089 remote-endpoint = <&dpu_intf0_out>;
3090 };
3091 };
3092
3093 port@1 {
3094 reg = <1>;
3095 dp_out: endpoint { };
3096 };
3097 };
3098
3099 dp_opp_table: opp-table {
3100 compatible = "operating-points-v2";
3101
3102 opp-160000000 {
3103 opp-hz = /bits/ 64 <160000000>;
3104 required-opps = <&rpmhpd_opp_low_svs>;
3105 };
3106
3107 opp-270000000 {
3108 opp-hz = /bits/ 64 <270000000>;
3109 required-opps = <&rpmhpd_opp_svs>;
3110 };
3111
3112 opp-540000000 {
3113 opp-hz = /bits/ 64 <540000000>;
3114 required-opps = <&rpmhpd_opp_svs_l1>;
3115 };
3116
3117 opp-810000000 {
3118 opp-hz = /bits/ 64 <810000000>;
3119 required-opps = <&rpmhpd_opp_nom>;
3120 };
3121 };
3122 };
3047 };
3048
3049 dispcc: clock-controller@af00000 {
3050 compatible = "qcom,sc7180-dispcc";
3051 reg = <0 0x0af00000 0 0x200000>;
3052 clocks = <&rpmhcc RPMH_CXO_CLK>,
3053 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3054 <&dsi_phy 0>,

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3124
3125 dispcc: clock-controller@af00000 {
3126 compatible = "qcom,sc7180-dispcc";
3127 reg = <0 0x0af00000 0 0x200000>;
3128 clocks = <&rpmhcc RPMH_CXO_CLK>,
3129 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3130 <&dsi_phy 0>,

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