sc7180.dtsi (320424c7d44f54c18df9812fd7c45f6963524002) sc7180.dtsi (f1b7e8976668075e6215191680cfb6a194b3c2ce)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,dispcc-sc7180.h>

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696 reg-names = "hc", "cqhci";
697
698 iommus = <&apps_smmu 0x60 0x0>;
699 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
701 interrupt-names = "hc_irq", "pwr_irq";
702
703 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,dispcc-sc7180.h>

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696 reg-names = "hc", "cqhci";
697
698 iommus = <&apps_smmu 0x60 0x0>;
699 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
701 interrupt-names = "hc_irq", "pwr_irq";
702
703 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
704 <&gcc GCC_SDCC1_AHB_CLK>;
705 clock-names = "core", "iface";
704 <&gcc GCC_SDCC1_AHB_CLK>,
705 <&rpmhcc RPMH_CXO_CLK>;
706 clock-names = "core", "iface", "xo";
706 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
707 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
708 interconnect-names = "sdhc-ddr","cpu-sdhc";
709 power-domains = <&rpmhpd SC7180_CX>;
710 operating-points-v2 = <&sdhc1_opp_table>;
711
712 bus-width = <8>;
713 non-removable;

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721 status = "disabled";
722
723 sdhc1_opp_table: sdhc1-opp-table {
724 compatible = "operating-points-v2";
725
726 opp-100000000 {
727 opp-hz = /bits/ 64 <100000000>;
728 required-opps = <&rpmhpd_opp_low_svs>;
707 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
708 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
709 interconnect-names = "sdhc-ddr","cpu-sdhc";
710 power-domains = <&rpmhpd SC7180_CX>;
711 operating-points-v2 = <&sdhc1_opp_table>;
712
713 bus-width = <8>;
714 non-removable;

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722 status = "disabled";
723
724 sdhc1_opp_table: sdhc1-opp-table {
725 compatible = "operating-points-v2";
726
727 opp-100000000 {
728 opp-hz = /bits/ 64 <100000000>;
729 required-opps = <&rpmhpd_opp_low_svs>;
729 opp-peak-kBps = <100000 100000>;
730 opp-avg-kBps = <100000 50000>;
730 opp-peak-kBps = <1800000 600000>;
731 opp-avg-kBps = <100000 0>;
731 };
732
733 opp-384000000 {
734 opp-hz = /bits/ 64 <384000000>;
732 };
733
734 opp-384000000 {
735 opp-hz = /bits/ 64 <384000000>;
735 required-opps = <&rpmhpd_opp_svs_l1>;
736 opp-peak-kBps = <600000 900000>;
737 opp-avg-kBps = <261438 300000>;
736 required-opps = <&rpmhpd_opp_nom>;
737 opp-peak-kBps = <5400000 1600000>;
738 opp-avg-kBps = <390000 0>;
738 };
739 };
740 };
741
742 qup_opp_table: qup-opp-table {
743 compatible = "operating-points-v2";
744
745 opp-75000000 {

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763 reg = <0 0x008c0000 0 0x6000>;
764 clock-names = "m-ahb", "s-ahb";
765 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
766 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
767 #address-cells = <2>;
768 #size-cells = <2>;
769 ranges;
770 iommus = <&apps_smmu 0x43 0x0>;
739 };
740 };
741 };
742
743 qup_opp_table: qup-opp-table {
744 compatible = "operating-points-v2";
745
746 opp-75000000 {

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764 reg = <0 0x008c0000 0 0x6000>;
765 clock-names = "m-ahb", "s-ahb";
766 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
767 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
768 #address-cells = <2>;
769 #size-cells = <2>;
770 ranges;
771 iommus = <&apps_smmu 0x43 0x0>;
771 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>;
772 interconnect-names = "qup-core";
773 status = "disabled";
774
775 i2c0: i2c@880000 {
776 compatible = "qcom,geni-i2c";
777 reg = <0 0x00880000 0 0x4000>;
778 clock-names = "se";
779 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
780 pinctrl-names = "default";

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1054 reg = <0 0x00ac0000 0 0x6000>;
1055 clock-names = "m-ahb", "s-ahb";
1056 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1057 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1058 #address-cells = <2>;
1059 #size-cells = <2>;
1060 ranges;
1061 iommus = <&apps_smmu 0x4c3 0x0>;
772 status = "disabled";
773
774 i2c0: i2c@880000 {
775 compatible = "qcom,geni-i2c";
776 reg = <0 0x00880000 0 0x4000>;
777 clock-names = "se";
778 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
779 pinctrl-names = "default";

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1053 reg = <0 0x00ac0000 0 0x6000>;
1054 clock-names = "m-ahb", "s-ahb";
1055 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1056 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1057 #address-cells = <2>;
1058 #size-cells = <2>;
1059 ranges;
1060 iommus = <&apps_smmu 0x4c3 0x0>;
1062 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>;
1063 interconnect-names = "qup-core";
1064 status = "disabled";
1065
1066 i2c6: i2c@a80000 {
1067 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00a80000 0 0x4000>;
1069 clock-names = "se";
1070 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1071 pinctrl-names = "default";

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1866 };
1867
1868 pri_mi2s_mclk_active: pri-mi2s-mclk-active {
1869 pinmux {
1870 pins = "gpio57";
1871 function = "lpass_ext";
1872 };
1873 };
1061 status = "disabled";
1062
1063 i2c6: i2c@a80000 {
1064 compatible = "qcom,geni-i2c";
1065 reg = <0 0x00a80000 0 0x4000>;
1066 clock-names = "se";
1067 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1068 pinctrl-names = "default";

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1863 };
1864
1865 pri_mi2s_mclk_active: pri-mi2s-mclk-active {
1866 pinmux {
1867 pins = "gpio57";
1868 function = "lpass_ext";
1869 };
1870 };
1874
1875 sdc1_on: sdc1-on {
1876 pinconf-clk {
1877 pins = "sdc1_clk";
1878 bias-disable;
1879 drive-strength = <16>;
1880 };
1881
1882 pinconf-cmd {
1883 pins = "sdc1_cmd";
1884 bias-pull-up;
1885 drive-strength = <10>;
1886 };
1887
1888 pinconf-data {
1889 pins = "sdc1_data";
1890 bias-pull-up;
1891 drive-strength = <10>;
1892 };
1893
1894 pinconf-rclk {
1895 pins = "sdc1_rclk";
1896 bias-pull-down;
1897 };
1898 };
1899
1900 sdc1_off: sdc1-off {
1901 pinconf-clk {
1902 pins = "sdc1_clk";
1903 bias-disable;
1904 drive-strength = <2>;
1905 };
1906
1907 pinconf-cmd {
1908 pins = "sdc1_cmd";
1909 bias-pull-up;
1910 drive-strength = <2>;
1911 };
1912
1913 pinconf-data {
1914 pins = "sdc1_data";
1915 bias-pull-up;
1916 drive-strength = <2>;
1917 };
1918
1919 pinconf-rclk {
1920 pins = "sdc1_rclk";
1921 bias-pull-down;
1922 };
1923 };
1924
1925 sdc2_on: sdc2-on {
1926 pinconf-clk {
1927 pins = "sdc2_clk";
1928 bias-disable;
1929 drive-strength = <16>;
1930 };
1931
1932 pinconf-cmd {
1933 pins = "sdc2_cmd";
1934 bias-pull-up;
1935 drive-strength = <10>;
1936 };
1937
1938 pinconf-data {
1939 pins = "sdc2_data";
1940 bias-pull-up;
1941 drive-strength = <10>;
1942 };
1943
1944 pinconf-sd-cd {
1945 pins = "gpio69";
1946 bias-pull-up;
1947 drive-strength = <2>;
1948 };
1949 };
1950
1951 sdc2_off: sdc2-off {
1952 pinconf-clk {
1953 pins = "sdc2_clk";
1954 bias-disable;
1955 drive-strength = <2>;
1956 };
1957
1958 pinconf-cmd {
1959 pins = "sdc2_cmd";
1960 bias-pull-up;
1961 drive-strength = <2>;
1962 };
1963
1964 pinconf-data {
1965 pins = "sdc2_data";
1966 bias-pull-up;
1967 drive-strength = <2>;
1968 };
1969
1970 pinconf-sd-cd {
1971 pins = "gpio69";
1972 bias-disable;
1973 drive-strength = <2>;
1974 };
1975 };
1976 };
1977
1978 remoteproc_mpss: remoteproc@4080000 {
1979 compatible = "qcom,sc7180-mpss-pas";
1980 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
1981 reg-names = "qdsp6", "rmb";
1982
1983 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,

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2665 reg = <0 0x08804000 0 0x1000>;
2666
2667 iommus = <&apps_smmu 0x80 0>;
2668 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2669 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2670 interrupt-names = "hc_irq", "pwr_irq";
2671
2672 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
1871 };
1872
1873 remoteproc_mpss: remoteproc@4080000 {
1874 compatible = "qcom,sc7180-mpss-pas";
1875 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
1876 reg-names = "qdsp6", "rmb";
1877
1878 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,

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2560 reg = <0 0x08804000 0 0x1000>;
2561
2562 iommus = <&apps_smmu 0x80 0>;
2563 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2564 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2565 interrupt-names = "hc_irq", "pwr_irq";
2566
2567 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2673 <&gcc GCC_SDCC2_AHB_CLK>;
2674 clock-names = "core", "iface";
2568 <&gcc GCC_SDCC2_AHB_CLK>,
2569 <&rpmhcc RPMH_CXO_CLK>;
2570 clock-names = "core", "iface", "xo";
2675
2676 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2677 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2678 interconnect-names = "sdhc-ddr","cpu-sdhc";
2679 power-domains = <&rpmhpd SC7180_CX>;
2680 operating-points-v2 = <&sdhc2_opp_table>;
2681
2682 bus-width = <4>;
2683
2684 status = "disabled";
2685
2686 sdhc2_opp_table: sdhc2-opp-table {
2687 compatible = "operating-points-v2";
2688
2689 opp-100000000 {
2690 opp-hz = /bits/ 64 <100000000>;
2691 required-opps = <&rpmhpd_opp_low_svs>;
2571
2572 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2573 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2574 interconnect-names = "sdhc-ddr","cpu-sdhc";
2575 power-domains = <&rpmhpd SC7180_CX>;
2576 operating-points-v2 = <&sdhc2_opp_table>;
2577
2578 bus-width = <4>;
2579
2580 status = "disabled";
2581
2582 sdhc2_opp_table: sdhc2-opp-table {
2583 compatible = "operating-points-v2";
2584
2585 opp-100000000 {
2586 opp-hz = /bits/ 64 <100000000>;
2587 required-opps = <&rpmhpd_opp_low_svs>;
2692 opp-peak-kBps = <160000 100000>;
2693 opp-avg-kBps = <80000 50000>;
2588 opp-peak-kBps = <1800000 600000>;
2589 opp-avg-kBps = <100000 0>;
2694 };
2695
2696 opp-202000000 {
2697 opp-hz = /bits/ 64 <202000000>;
2590 };
2591
2592 opp-202000000 {
2593 opp-hz = /bits/ 64 <202000000>;
2698 required-opps = <&rpmhpd_opp_svs_l1>;
2699 opp-peak-kBps = <200000 120000>;
2700 opp-avg-kBps = <100000 60000>;
2594 required-opps = <&rpmhpd_opp_nom>;
2595 opp-peak-kBps = <5400000 1600000>;
2596 opp-avg-kBps = <200000 0>;
2701 };
2702 };
2703 };
2704
2705 qspi_opp_table: qspi-opp-table {
2706 compatible = "operating-points-v2";
2707
2708 opp-75000000 {

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2749 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2750
2751 nvmem-cells = <&qusb2p_hstx_trim>;
2752 };
2753
2754 usb_1_qmpphy: phy-wrapper@88e9000 {
2755 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2756 reg = <0 0x088e9000 0 0x18c>,
2597 };
2598 };
2599 };
2600
2601 qspi_opp_table: qspi-opp-table {
2602 compatible = "operating-points-v2";
2603
2604 opp-75000000 {

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2645 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2646
2647 nvmem-cells = <&qusb2p_hstx_trim>;
2648 };
2649
2650 usb_1_qmpphy: phy-wrapper@88e9000 {
2651 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2652 reg = <0 0x088e9000 0 0x18c>,
2757 <0 0x088e8000 0 0x38>,
2758 <0 0x088ea000 0 0x40>;
2653 <0 0x088e8000 0 0x3c>,
2654 <0 0x088ea000 0 0x18c>;
2759 status = "disabled";
2760 #address-cells = <2>;
2761 #size-cells = <2>;
2762 ranges;
2763
2764 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2765 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2766 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,

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2855 power-domains = <&gcc USB30_PRIM_GDSC>;
2856
2857 resets = <&gcc GCC_USB30_PRIM_BCR>;
2858
2859 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2860 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2861 interconnect-names = "usb-ddr", "apps-usb";
2862
2655 status = "disabled";
2656 #address-cells = <2>;
2657 #size-cells = <2>;
2658 ranges;
2659
2660 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2661 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2662 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,

--- 88 unchanged lines hidden (view full) ---

2751 power-domains = <&gcc USB30_PRIM_GDSC>;
2752
2753 resets = <&gcc GCC_USB30_PRIM_BCR>;
2754
2755 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2756 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2757 interconnect-names = "usb-ddr", "apps-usb";
2758
2863 usb_1_dwc3: dwc3@a600000 {
2759 usb_1_dwc3: usb@a600000 {
2864 compatible = "snps,dwc3";
2865 reg = <0 0x0a600000 0 0xe000>;
2866 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2867 iommus = <&apps_smmu 0x540 0>;
2868 snps,dis_u2_susphy_quirk;
2869 snps,dis_enblslpm_quirk;
2870 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2871 phy-names = "usb2-phy", "usb3-phy";

--- 155 unchanged lines hidden (view full) ---

3027 #size-cells = <0>;
3028
3029 port@0 {
3030 reg = <0>;
3031 dpu_intf1_out: endpoint {
3032 remote-endpoint = <&dsi0_in>;
3033 };
3034 };
2760 compatible = "snps,dwc3";
2761 reg = <0 0x0a600000 0 0xe000>;
2762 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2763 iommus = <&apps_smmu 0x540 0>;
2764 snps,dis_u2_susphy_quirk;
2765 snps,dis_enblslpm_quirk;
2766 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2767 phy-names = "usb2-phy", "usb3-phy";

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2923 #size-cells = <0>;
2924
2925 port@0 {
2926 reg = <0>;
2927 dpu_intf1_out: endpoint {
2928 remote-endpoint = <&dsi0_in>;
2929 };
2930 };
2931
2932 port@2 {
2933 reg = <2>;
2934 dpu_intf0_out: endpoint {
2935 remote-endpoint = <&dp_in>;
2936 };
2937 };
3035 };
3036
3037 mdp_opp_table: mdp-opp-table {
3038 compatible = "operating-points-v2";
3039
3040 opp-200000000 {
3041 opp-hz = /bits/ 64 <200000000>;
3042 required-opps = <&rpmhpd_opp_low_svs>;

--- 100 unchanged lines hidden (view full) ---

3143 #phy-cells = <0>;
3144
3145 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3146 <&rpmhcc RPMH_CXO_CLK>;
3147 clock-names = "iface", "ref";
3148
3149 status = "disabled";
3150 };
2938 };
2939
2940 mdp_opp_table: mdp-opp-table {
2941 compatible = "operating-points-v2";
2942
2943 opp-200000000 {
2944 opp-hz = /bits/ 64 <200000000>;
2945 required-opps = <&rpmhpd_opp_low_svs>;

--- 100 unchanged lines hidden (view full) ---

3046 #phy-cells = <0>;
3047
3048 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3049 <&rpmhcc RPMH_CXO_CLK>;
3050 clock-names = "iface", "ref";
3051
3052 status = "disabled";
3053 };
3054
3055 mdss_dp: displayport-controller@ae90000 {
3056 compatible = "qcom,sc7180-dp";
3057 status = "disabled";
3058
3059 reg = <0 0x0ae90000 0 0x1400>;
3060
3061 interrupt-parent = <&mdss>;
3062 interrupts = <12>;
3063
3064 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3065 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3066 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3067 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3068 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3069 clock-names = "core_iface", "core_aux", "ctrl_link",
3070 "ctrl_link_iface", "stream_pixel";
3071 #clock-cells = <1>;
3072 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3073 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3074 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3075 phys = <&dp_phy>;
3076 phy-names = "dp";
3077
3078 operating-points-v2 = <&dp_opp_table>;
3079 power-domains = <&rpmhpd SC7180_CX>;
3080
3081 #sound-dai-cells = <0>;
3082
3083 ports {
3084 #address-cells = <1>;
3085 #size-cells = <0>;
3086 port@0 {
3087 reg = <0>;
3088 dp_in: endpoint {
3089 remote-endpoint = <&dpu_intf0_out>;
3090 };
3091 };
3092
3093 port@1 {
3094 reg = <1>;
3095 dp_out: endpoint { };
3096 };
3097 };
3098
3099 dp_opp_table: opp-table {
3100 compatible = "operating-points-v2";
3101
3102 opp-160000000 {
3103 opp-hz = /bits/ 64 <160000000>;
3104 required-opps = <&rpmhpd_opp_low_svs>;
3105 };
3106
3107 opp-270000000 {
3108 opp-hz = /bits/ 64 <270000000>;
3109 required-opps = <&rpmhpd_opp_svs>;
3110 };
3111
3112 opp-540000000 {
3113 opp-hz = /bits/ 64 <540000000>;
3114 required-opps = <&rpmhpd_opp_svs_l1>;
3115 };
3116
3117 opp-810000000 {
3118 opp-hz = /bits/ 64 <810000000>;
3119 required-opps = <&rpmhpd_opp_nom>;
3120 };
3121 };
3122 };
3151 };
3152
3153 dispcc: clock-controller@af00000 {
3154 compatible = "qcom,sc7180-dispcc";
3155 reg = <0 0x0af00000 0 0x200000>;
3156 clocks = <&rpmhcc RPMH_CXO_CLK>,
3157 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3158 <&dsi_phy 0>,

--- 1241 unchanged lines hidden --- 		3123 };
3124
3125 dispcc: clock-controller@af00000 {
3126 compatible = "qcom,sc7180-dispcc";
3127 reg = <0 0x0af00000 0 0x200000>;
3128 clocks = <&rpmhcc RPMH_CXO_CLK>,
3129 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3130 <&dsi_phy 0>,

--- 1241 unchanged lines hidden ---