tegra194.dtsi (f69ce393ec48a759e5df4ea6660fb7662f24197c) tegra194.dtsi (f89b58ce71a949ca3592728b586d2077b6cc7ecc)
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra194-clock.h>
3#include <dt-bindings/gpio/tegra194-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/reset/tegra194-reset.h>
7
8/ {

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30 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
32 #interrupt-cells = <2>;
33 interrupt-controller;
34 #gpio-cells = <2>;
35 gpio-controller;
36 };
37
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra194-clock.h>
3#include <dt-bindings/gpio/tegra194-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/reset/tegra194-reset.h>
7
8/ {

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30 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
32 #interrupt-cells = <2>;
33 interrupt-controller;
34 #gpio-cells = <2>;
35 gpio-controller;
36 };
37
38 ethernet@2490000 {
39 compatible = "nvidia,tegra186-eqos",
40 "snps,dwc-qos-ethernet-4.10";
41 reg = <0x02490000 0x10000>;
42 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
43 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
44 <&bpmp TEGRA194_CLK_EQOS_AXI>,
45 <&bpmp TEGRA194_CLK_EQOS_RX>,
46 <&bpmp TEGRA194_CLK_EQOS_TX>,
47 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
48 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
49 resets = <&bpmp TEGRA194_RESET_EQOS>;
50 reset-names = "eqos";
51 status = "disabled";
52
53 snps,write-requests = <1>;
54 snps,read-requests = <3>;
55 snps,burst-map = <0x7>;
56 snps,txpbl = <16>;
57 snps,rxpbl = <8>;
58 };
59
38 uarta: serial@3100000 {
39 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
40 reg = <0x03100000 0x40>;
41 reg-shift = <2>;
42 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
43 clocks = <&bpmp TEGRA194_CLK_UARTA>;
44 clock-names = "serial";
45 resets = <&bpmp TEGRA194_RESET_UARTA>;

--- 316 unchanged lines hidden --- 		60 uarta: serial@3100000 {
61 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
62 reg = <0x03100000 0x40>;
63 reg-shift = <2>;
64 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
65 clocks = <&bpmp TEGRA194_CLK_UARTA>;
66 clock-names = "serial";
67 resets = <&bpmp TEGRA194_RESET_UARTA>;

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