tegra194.dtsi (052d3f6523044cd7d6136e743d286a7ca1604c15) tegra194.dtsi (67bb17f6109eb86fa752f70741e47404357bc7c6)
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra194-clock.h>
3#include <dt-bindings/gpio/tegra194-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/pinctrl/pinctrl-tegra.h>
7#include <dt-bindings/power/tegra194-powergate.h>
8#include <dt-bindings/reset/tegra194-reset.h>

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451 clocks = <&bpmp TEGRA194_CLK_PWM8>;
452 clock-names = "pwm";
453 resets = <&bpmp TEGRA194_RESET_PWM8>;
454 reset-names = "pwm";
455 status = "disabled";
456 #pwm-cells = <2>;
457 };
458
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra194-clock.h>
3#include <dt-bindings/gpio/tegra194-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/pinctrl/pinctrl-tegra.h>
7#include <dt-bindings/power/tegra194-powergate.h>
8#include <dt-bindings/reset/tegra194-reset.h>

--- 442 unchanged lines hidden (view full) ---

451 clocks = <&bpmp TEGRA194_CLK_PWM8>;
452 clock-names = "pwm";
453 resets = <&bpmp TEGRA194_RESET_PWM8>;
454 reset-names = "pwm";
455 status = "disabled";
456 #pwm-cells = <2>;
457 };
458
459 sdmmc1: sdhci@3400000 {
459 sdmmc1: mmc@3400000 {
460 compatible = "nvidia,tegra194-sdhci";
461 reg = <0x03400000 0x10000>;
462 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
464 clock-names = "sdhci";
465 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
466 reset-names = "sdhci";
467 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,

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476 <0x07>;
477 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
478 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
479 nvidia,default-tap = <0x9>;
480 nvidia,default-trim = <0x5>;
481 status = "disabled";
482 };
483
460 compatible = "nvidia,tegra194-sdhci";
461 reg = <0x03400000 0x10000>;
462 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
464 clock-names = "sdhci";
465 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
466 reset-names = "sdhci";
467 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,

--- 8 unchanged lines hidden (view full) ---

476 <0x07>;
477 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
478 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
479 nvidia,default-tap = <0x9>;
480 nvidia,default-trim = <0x5>;
481 status = "disabled";
482 };
483
484 sdmmc3: sdhci@3440000 {
484 sdmmc3: mmc@3440000 {
485 compatible = "nvidia,tegra194-sdhci";
486 reg = <0x03440000 0x10000>;
487 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
489 clock-names = "sdhci";
490 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
491 reset-names = "sdhci";
492 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,

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502 <0x07>;
503 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
504 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
505 nvidia,default-tap = <0x9>;
506 nvidia,default-trim = <0x5>;
507 status = "disabled";
508 };
509
485 compatible = "nvidia,tegra194-sdhci";
486 reg = <0x03440000 0x10000>;
487 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
489 clock-names = "sdhci";
490 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
491 reset-names = "sdhci";
492 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,

--- 9 unchanged lines hidden (view full) ---

502 <0x07>;
503 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
504 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
505 nvidia,default-tap = <0x9>;
506 nvidia,default-trim = <0x5>;
507 status = "disabled";
508 };
509
510 sdmmc4: sdhci@3460000 {
510 sdmmc4: mmc@3460000 {
511 compatible = "nvidia,tegra194-sdhci";
512 reg = <0x03460000 0x10000>;
513 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
515 clock-names = "sdhci";
516 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
517 <&bpmp TEGRA194_CLK_PLLC4>;
518 assigned-clock-parents =

--- 1595 unchanged lines hidden --- 		511 compatible = "nvidia,tegra194-sdhci";
512 reg = <0x03460000 0x10000>;
513 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
515 clock-names = "sdhci";
516 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
517 <&bpmp TEGRA194_CLK_PLLC4>;
518 assigned-clock-parents =

--- 1595 unchanged lines hidden ---