mt8195.dtsi (f777316e52e14059a6a1df45cbf39a93ac49a593) mt8195.dtsi (ab43a84c9863b65dc20373d5aca4e4d012aa852e)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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686 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
687 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
688 clock-names = "spi", "sf", "axi";
689 #address-cells = <1>;
690 #size-cells = <0>;
691 status = "disabled";
692 };
693
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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686 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
687 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
688 clock-names = "spi", "sf", "axi";
689 #address-cells = <1>;
690 #size-cells = <0>;
691 status = "disabled";
692 };
693
694 efuse: efuse@11c10000 {
695 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
696 reg = <0 0x11c10000 0 0x1000>;
697 #address-cells = <1>;
698 #size-cells = <1>;
699 u3_tx_imp_p0: usb3-tx-imp@184,1 {
700 reg = <0x184 0x1>;
701 bits = <0 5>;
702 };
703 u3_rx_imp_p0: usb3-rx-imp@184,2 {
704 reg = <0x184 0x2>;
705 bits = <5 5>;
706 };
707 u3_intr_p0: usb3-intr@185 {
708 reg = <0x185 0x1>;
709 bits = <2 6>;
710 };
711 comb_tx_imp_p1: usb3-tx-imp@186,1 {
712 reg = <0x186 0x1>;
713 bits = <0 5>;
714 };
715 comb_rx_imp_p1: usb3-rx-imp@186,2 {
716 reg = <0x186 0x2>;
717 bits = <5 5>;
718 };
719 comb_intr_p1: usb3-intr@187 {
720 reg = <0x187 0x1>;
721 bits = <2 6>;
722 };
723 u2_intr_p0: usb2-intr-p0@188,1 {
724 reg = <0x188 0x1>;
725 bits = <0 5>;
726 };
727 u2_intr_p1: usb2-intr-p1@188,2 {
728 reg = <0x188 0x2>;
729 bits = <5 5>;
730 };
731 u2_intr_p2: usb2-intr-p2@189,1 {
732 reg = <0x189 0x1>;
733 bits = <2 5>;
734 };
735 u2_intr_p3: usb2-intr-p3@189,2 {
736 reg = <0x189 0x2>;
737 bits = <7 5>;
738 };
739 };
740
694 u3phy2: t-phy@11c40000 {
695 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
696 #address-cells = <1>;
697 #size-cells = <1>;
698 ranges = <0 0 0x11c40000 0x700>;
699 status = "disabled";
700
701 u2port2: usb-phy@0 {

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868 #phy-cells = <1>;
869 };
870
871 u3port1: usb-phy@700 {
872 reg = <0x700 0x700>;
873 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
874 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
875 clock-names = "ref", "da_ref";
741 u3phy2: t-phy@11c40000 {
742 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
743 #address-cells = <1>;
744 #size-cells = <1>;
745 ranges = <0 0 0x11c40000 0x700>;
746 status = "disabled";
747
748 u2port2: usb-phy@0 {

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915 #phy-cells = <1>;
916 };
917
918 u3port1: usb-phy@700 {
919 reg = <0x700 0x700>;
920 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
921 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
922 clock-names = "ref", "da_ref";
923 nvmem-cells = <&comb_intr_p1>,
924 <&comb_rx_imp_p1>,
925 <&comb_tx_imp_p1>;
926 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
876 #phy-cells = <1>;
877 };
878 };
879
880 u3phy0: t-phy@11e40000 {
881 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
882 #address-cells = <1>;
883 #size-cells = <1>;

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892 #phy-cells = <1>;
893 };
894
895 u3port0: usb-phy@700 {
896 reg = <0x700 0x700>;
897 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
898 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
899 clock-names = "ref", "da_ref";
927 #phy-cells = <1>;
928 };
929 };
930
931 u3phy0: t-phy@11e40000 {
932 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
933 #address-cells = <1>;
934 #size-cells = <1>;

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943 #phy-cells = <1>;
944 };
945
946 u3port0: usb-phy@700 {
947 reg = <0x700 0x700>;
948 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
949 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
950 clock-names = "ref", "da_ref";
951 nvmem-cells = <&u3_intr_p0>,
952 <&u3_rx_imp_p0>,
953 <&u3_tx_imp_p0>;
954 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
900 #phy-cells = <1>;
901 };
902 };
903
904 ufsphy: ufs-phy@11fa0000 {
905 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
906 reg = <0 0x11fa0000 0 0xc000>;
907 clocks = <&clk26m>, <&clk26m>;

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956 };
957 };
958
959 ufsphy: ufs-phy@11fa0000 {
960 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
961 reg = <0 0x11fa0000 0 0xc000>;
962 clocks = <&clk26m>, <&clk26m>;

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