mt8195.dtsi (db6da59cf27b5661ced03754ae0550f8914eda9e) mt8195.dtsi (64bceed383fbce8ef54200d2849935096fe8f831)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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19
20/ {
21 compatible = "mediatek,mt8195";
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 aliases {
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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19
20/ {
21 compatible = "mediatek,mt8195";
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 aliases {
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
27 gce0 = &gce0;
28 gce1 = &gce1;
29 ethdr0 = &ethdr0;
30 mutex0 = &mutex;
31 mutex1 = &mutex1;
32 merge1 = &merge1;
33 merge2 = &merge2;
34 merge3 = &merge3;

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278
279 l2_0: l2-cache0 {
280 compatible = "cache";
281 cache-level = <2>;
282 cache-size = <131072>;
283 cache-line-size = <64>;
284 cache-sets = <512>;
285 next-level-cache = <&l3_0>;
29 gce0 = &gce0;
30 gce1 = &gce1;
31 ethdr0 = &ethdr0;
32 mutex0 = &mutex;
33 mutex1 = &mutex1;
34 merge1 = &merge1;
35 merge2 = &merge2;
36 merge3 = &merge3;

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280
281 l2_0: l2-cache0 {
282 compatible = "cache";
283 cache-level = <2>;
284 cache-size = <131072>;
285 cache-line-size = <64>;
286 cache-sets = <512>;
287 next-level-cache = <&l3_0>;
288 cache-unified;
286 };
287
288 l2_1: l2-cache1 {
289 compatible = "cache";
290 cache-level = <2>;
291 cache-size = <262144>;
292 cache-line-size = <64>;
293 cache-sets = <512>;
294 next-level-cache = <&l3_0>;
289 };
290
291 l2_1: l2-cache1 {
292 compatible = "cache";
293 cache-level = <2>;
294 cache-size = <262144>;
295 cache-line-size = <64>;
296 cache-sets = <512>;
297 next-level-cache = <&l3_0>;
298 cache-unified;
295 };
296
297 l3_0: l3-cache {
298 compatible = "cache";
299 cache-level = <3>;
300 cache-size = <2097152>;
301 cache-line-size = <64>;
302 cache-sets = <2048>;

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2361 mediatek,larb-id = <18>;
2362 mediatek,smi = <&smi_sub_common_cam_7x1>;
2363 clocks = <&ccusys CLK_CCU_LARB18>,
2364 <&ccusys CLK_CCU_LARB18>;
2365 clock-names = "apb", "smi";
2366 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2367 };
2368
299 };
300
301 l3_0: l3-cache {
302 compatible = "cache";
303 cache-level = <3>;
304 cache-size = <2097152>;
305 cache-line-size = <64>;
306 cache-sets = <2048>;

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2365 mediatek,larb-id = <18>;
2366 mediatek,smi = <&smi_sub_common_cam_7x1>;
2367 clocks = <&ccusys CLK_CCU_LARB18>,
2368 <&ccusys CLK_CCU_LARB18>;
2369 clock-names = "apb", "smi";
2370 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2371 };
2372
2373 video-codec@18000000 {
2374 compatible = "mediatek,mt8195-vcodec-dec";
2375 mediatek,scp = <&scp>;
2376 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>;
2377 #address-cells = <2>;
2378 #size-cells = <2>;
2379 reg = <0 0x18000000 0 0x1000>,
2380 <0 0x18004000 0 0x1000>;
2381 ranges = <0 0 0 0x18000000 0 0x26000>;
2382
2383 video-codec@2000 {
2384 compatible = "mediatek,mtk-vcodec-lat-soc";
2385 reg = <0 0x2000 0 0x800>;
2386 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>,
2387 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>;
2388 clocks = <&topckgen CLK_TOP_VDEC>,
2389 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
2390 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
2391 <&topckgen CLK_TOP_UNIVPLL_D4>;
2392 clock-names = "sel", "vdec", "lat", "top";
2393 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2394 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2395 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2396 };
2397
2398 video-codec@10000 {
2399 compatible = "mediatek,mtk-vcodec-lat";
2400 reg = <0 0x10000 0 0x800>;
2401 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>;
2402 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>,
2403 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>,
2404 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>,
2405 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>,
2406 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>,
2407 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>;
2408 clocks = <&topckgen CLK_TOP_VDEC>,
2409 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
2410 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
2411 <&topckgen CLK_TOP_UNIVPLL_D4>;
2412 clock-names = "sel", "vdec", "lat", "top";
2413 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2414 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2415 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2416 };
2417
2418 video-codec@25000 {
2419 compatible = "mediatek,mtk-vcodec-core";
2420 reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */
2421 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>;
2422 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>,
2423 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>,
2424 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>,
2425 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>,
2426 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>,
2427 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>,
2428 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>,
2429 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>,
2430 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>,
2431 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>;
2432 clocks = <&topckgen CLK_TOP_VDEC>,
2433 <&vdecsys CLK_VDEC_VDEC>,
2434 <&vdecsys CLK_VDEC_LAT>,
2435 <&topckgen CLK_TOP_UNIVPLL_D4>;
2436 clock-names = "sel", "vdec", "lat", "top";
2437 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2438 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2439 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2440 };
2441 };
2442
2369 larb24: larb@1800d000 {
2370 compatible = "mediatek,mt8195-smi-larb";
2371 reg = <0 0x1800d000 0 0x1000>;
2372 mediatek,larb-id = <24>;
2373 mediatek,smi = <&smi_common_vdo>;
2374 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
2375 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2376 clock-names = "apb", "smi";

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3257 trip = <&cpu7_alert>;
3258 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3259 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3260 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3261 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3262 };
3263 };
3264 };
2443 larb24: larb@1800d000 {
2444 compatible = "mediatek,mt8195-smi-larb";
2445 reg = <0 0x1800d000 0 0x1000>;
2446 mediatek,larb-id = <24>;
2447 mediatek,smi = <&smi_common_vdo>;
2448 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
2449 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2450 clock-names = "apb", "smi";

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3331 trip = <&cpu7_alert>;
3332 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3333 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3334 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3335 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3336 };
3337 };
3338 };
3339
3340 vpu0-thermal {
3341 polling-delay = <1000>;
3342 polling-delay-passive = <250>;
3343 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
3344
3345 trips {
3346 vpu0_alert: trip-alert {
3347 temperature = <85000>;
3348 hysteresis = <2000>;
3349 type = "passive";
3350 };
3351
3352 vpu0_crit: trip-crit {
3353 temperature = <100000>;
3354 hysteresis = <2000>;
3355 type = "critical";
3356 };
3357 };
3358 };
3359
3360 vpu1-thermal {
3361 polling-delay = <1000>;
3362 polling-delay-passive = <250>;
3363 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
3364
3365 trips {
3366 vpu1_alert: trip-alert {
3367 temperature = <85000>;
3368 hysteresis = <2000>;
3369 type = "passive";
3370 };
3371
3372 vpu1_crit: trip-crit {
3373 temperature = <100000>;
3374 hysteresis = <2000>;
3375 type = "critical";
3376 };
3377 };
3378 };
3379
3380 gpu0-thermal {
3381 polling-delay = <1000>;
3382 polling-delay-passive = <250>;
3383 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
3384
3385 trips {
3386 gpu0_alert: trip-alert {
3387 temperature = <85000>;
3388 hysteresis = <2000>;
3389 type = "passive";
3390 };
3391
3392 gpu0_crit: trip-crit {
3393 temperature = <100000>;
3394 hysteresis = <2000>;
3395 type = "critical";
3396 };
3397 };
3398 };
3399
3400 gpu1-thermal {
3401 polling-delay = <1000>;
3402 polling-delay-passive = <250>;
3403 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
3404
3405 trips {
3406 gpu1_alert: trip-alert {
3407 temperature = <85000>;
3408 hysteresis = <2000>;
3409 type = "passive";
3410 };
3411
3412 gpu1_crit: trip-crit {
3413 temperature = <100000>;
3414 hysteresis = <2000>;
3415 type = "critical";
3416 };
3417 };
3418 };
3419
3420 vdec-thermal {
3421 polling-delay = <1000>;
3422 polling-delay-passive = <250>;
3423 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
3424
3425 trips {
3426 vdec_alert: trip-alert {
3427 temperature = <85000>;
3428 hysteresis = <2000>;
3429 type = "passive";
3430 };
3431
3432 vdec_crit: trip-crit {
3433 temperature = <100000>;
3434 hysteresis = <2000>;
3435 type = "critical";
3436 };
3437 };
3438 };
3439
3440 img-thermal {
3441 polling-delay = <1000>;
3442 polling-delay-passive = <250>;
3443 thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
3444
3445 trips {
3446 img_alert: trip-alert {
3447 temperature = <85000>;
3448 hysteresis = <2000>;
3449 type = "passive";
3450 };
3451
3452 img_crit: trip-crit {
3453 temperature = <100000>;
3454 hysteresis = <2000>;
3455 type = "critical";
3456 };
3457 };
3458 };
3459
3460 infra-thermal {
3461 polling-delay = <1000>;
3462 polling-delay-passive = <250>;
3463 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
3464
3465 trips {
3466 infra_alert: trip-alert {
3467 temperature = <85000>;
3468 hysteresis = <2000>;
3469 type = "passive";
3470 };
3471
3472 infra_crit: trip-crit {
3473 temperature = <100000>;
3474 hysteresis = <2000>;
3475 type = "critical";
3476 };
3477 };
3478 };
3479
3480 cam0-thermal {
3481 polling-delay = <1000>;
3482 polling-delay-passive = <250>;
3483 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
3484
3485 trips {
3486 cam0_alert: trip-alert {
3487 temperature = <85000>;
3488 hysteresis = <2000>;
3489 type = "passive";
3490 };
3491
3492 cam0_crit: trip-crit {
3493 temperature = <100000>;
3494 hysteresis = <2000>;
3495 type = "critical";
3496 };
3497 };
3498 };
3499
3500 cam1-thermal {
3501 polling-delay = <1000>;
3502 polling-delay-passive = <250>;
3503 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
3504
3505 trips {
3506 cam1_alert: trip-alert {
3507 temperature = <85000>;
3508 hysteresis = <2000>;
3509 type = "passive";
3510 };
3511
3512 cam1_crit: trip-crit {
3513 temperature = <100000>;
3514 hysteresis = <2000>;
3515 type = "critical";
3516 };
3517 };
3518 };
3265 };
3266};
3519 };
3520};