mt8195.dtsi (d93618da6b6d453c6a9684a3460ffd51b9b4ef2e) mt8195.dtsi (ce459b1da752cf1dc0b81aba999a6542ab866993)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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208 entry-latency-us = <50>;
209 exit-latency-us = <200>;
210 min-residency-us = <1000>;
211 };
212 };
213
214 l2_0: l2-cache0 {
215 compatible = "cache";
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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208 entry-latency-us = <50>;
209 exit-latency-us = <200>;
210 min-residency-us = <1000>;
211 };
212 };
213
214 l2_0: l2-cache0 {
215 compatible = "cache";
216 cache-level = <2>;
216 next-level-cache = <&l3_0>;
217 };
218
219 l2_1: l2-cache1 {
220 compatible = "cache";
217 next-level-cache = <&l3_0>;
218 };
219
220 l2_1: l2-cache1 {
221 compatible = "cache";
222 cache-level = <2>;
221 next-level-cache = <&l3_0>;
222 };
223
224 l3_0: l3-cache {
225 compatible = "cache";
223 next-level-cache = <&l3_0>;
224 };
225
226 l3_0: l3-cache {
227 compatible = "cache";
228 cache-level = <3>;
226 };
227 };
228
229 dsu-pmu {
230 compatible = "arm,dsu-pmu";
231 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
232 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
233 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;

--- 1926 unchanged lines hidden --- 		229 };
230 };
231
232 dsu-pmu {
233 compatible = "arm,dsu-pmu";
234 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
235 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
236 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;

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