mt8195.dtsi (d0e99511834b6828c960e978d9a8cb6e5731250d) mt8195.dtsi (97801cfcf9565247bcc53b67ea47fa87b1704375)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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2141
2142 vencsys_core1: clock-controller@1b000000 {
2143 compatible = "mediatek,mt8195-vencsys_core1";
2144 reg = <0 0x1b000000 0 0x1000>;
2145 #clock-cells = <1>;
2146 };
2147
2148 vdosys0: syscon@1c01a000 {
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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2141
2142 vencsys_core1: clock-controller@1b000000 {
2143 compatible = "mediatek,mt8195-vencsys_core1";
2144 reg = <0 0x1b000000 0 0x1000>;
2145 #clock-cells = <1>;
2146 };
2147
2148 vdosys0: syscon@1c01a000 {
2149 compatible = "mediatek,mt8195-mmsys", "syscon";
2149 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
2150 reg = <0 0x1c01a000 0 0x1000>;
2151 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
2152 #clock-cells = <1>;
2153 };
2154
2155 larb20: larb@1b010000 {
2156 compatible = "mediatek,mt8195-smi-larb";
2157 reg = <0 0x1b010000 0 0x1000>;

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2287 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
2288 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
2289 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
2290 clock-names = "apb", "smi", "gals";
2291 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2292 };
2293
2294 vdosys1: syscon@1c100000 {
2150 reg = <0 0x1c01a000 0 0x1000>;
2151 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
2152 #clock-cells = <1>;
2153 };
2154
2155 larb20: larb@1b010000 {
2156 compatible = "mediatek,mt8195-smi-larb";
2157 reg = <0 0x1b010000 0 0x1000>;

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2287 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
2288 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
2289 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
2290 clock-names = "apb", "smi", "gals";
2291 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2292 };
2293
2294 vdosys1: syscon@1c100000 {
2295 compatible = "mediatek,mt8195-mmsys", "syscon";
2295 compatible = "mediatek,mt8195-vdosys1", "syscon";
2296 reg = <0 0x1c100000 0 0x1000>;
2297 #clock-cells = <1>;
2298 };
2299
2300 smi_common_vdo: smi@1c01b000 {
2301 compatible = "mediatek,mt8195-smi-common-vdo";
2302 reg = <0 0x1c01b000 0 0x1000>;
2303 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,

--- 81 unchanged lines hidden --- 		2296 reg = <0 0x1c100000 0 0x1000>;
2297 #clock-cells = <1>;
2298 };
2299
2300 smi_common_vdo: smi@1c01b000 {
2301 compatible = "mediatek,mt8195-smi-common-vdo";
2302 reg = <0 0x1c01b000 0 0x1000>;
2303 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,

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