mt8195.dtsi (c5fe37e8528ffb191baa7244ab33b8deaae6a4b7) mt8195.dtsi (89b045d3c2cdffbb62f81c659e69653d862feee3)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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1534 };
1535 pciephy_glb_intr: pciephy-glb-intr@193 {
1536 reg = <0x193 0x1>;
1537 bits = <0 4>;
1538 };
1539 dp_calibration: dp-data@1ac {
1540 reg = <0x1ac 0x10>;
1541 };
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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1534 };
1535 pciephy_glb_intr: pciephy-glb-intr@193 {
1536 reg = <0x193 0x1>;
1537 bits = <0 4>;
1538 };
1539 dp_calibration: dp-data@1ac {
1540 reg = <0x1ac 0x10>;
1541 };
1542 lvts_efuse_data1: lvts1-calib@1bc {
1543 reg = <0x1bc 0x14>;
1544 };
1545 lvts_efuse_data2: lvts2-calib@1d0 {
1546 reg = <0x1d0 0x38>;
1547 };
1542 };
1543
1544 u3phy2: t-phy@11c40000 {
1545 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1546 #address-cells = <1>;
1547 #size-cells = <1>;
1548 ranges = <0 0 0x11c40000 0x700>;
1549 status = "disabled";

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1549
1550 u3phy2: t-phy@11c40000 {
1551 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1552 #address-cells = <1>;
1553 #size-cells = <1>;
1554 ranges = <0 0 0x11c40000 0x700>;
1555 status = "disabled";

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