mt8195.dtsi (981f808e641c624fdf4ece806b599ae66e875ee4) mt8195.dtsi (018f1d4fa457af98c9618c0bd17a427745f872fa)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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1796 };
1797
1798 vppsys0: syscon@14000000 {
1799 compatible = "mediatek,mt8195-vppsys0", "syscon";
1800 reg = <0 0x14000000 0 0x1000>;
1801 #clock-cells = <1>;
1802 };
1803
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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1796 };
1797
1798 vppsys0: syscon@14000000 {
1799 compatible = "mediatek,mt8195-vppsys0", "syscon";
1800 reg = <0 0x14000000 0 0x1000>;
1801 #clock-cells = <1>;
1802 };
1803
1804 mutex@1400f000 {
1805 compatible = "mediatek,mt8195-vpp-mutex";
1806 reg = <0 0x1400f000 0 0x1000>;
1807 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
1808 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
1809 clocks = <&vppsys0 CLK_VPP0_MUTEX>;
1810 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1811 };
1812
1804 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
1805 compatible = "mediatek,mt8195-smi-sub-common";
1806 reg = <0 0x14010000 0 0x1000>;
1807 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1808 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1809 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
1810 clock-names = "apb", "smi", "gals0";
1811 mediatek,smi = <&smi_common_vpp>;

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1901 };
1902
1903 vppsys1: syscon@14f00000 {
1904 compatible = "mediatek,mt8195-vppsys1", "syscon";
1905 reg = <0 0x14f00000 0 0x1000>;
1906 #clock-cells = <1>;
1907 };
1908
1813 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
1814 compatible = "mediatek,mt8195-smi-sub-common";
1815 reg = <0 0x14010000 0 0x1000>;
1816 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1817 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1818 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
1819 clock-names = "apb", "smi", "gals0";
1820 mediatek,smi = <&smi_common_vpp>;

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1910 };
1911
1912 vppsys1: syscon@14f00000 {
1913 compatible = "mediatek,mt8195-vppsys1", "syscon";
1914 reg = <0 0x14f00000 0 0x1000>;
1915 #clock-cells = <1>;
1916 };
1917
1918 mutex@14f01000 {
1919 compatible = "mediatek,mt8195-vpp-mutex";
1920 reg = <0 0x14f01000 0 0x1000>;
1921 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
1922 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
1923 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
1924 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
1925 };
1926
1909 larb5: larb@14f02000 {
1910 compatible = "mediatek,mt8195-smi-larb";
1911 reg = <0 0x14f02000 0 0x1000>;
1912 mediatek,larb-id = <5>;
1913 mediatek,smi = <&smi_common_vdo>;
1914 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
1915 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
1916 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;

--- 731 unchanged lines hidden --- 		1927 larb5: larb@14f02000 {
1928 compatible = "mediatek,mt8195-smi-larb";
1929 reg = <0 0x14f02000 0 0x1000>;
1930 mediatek,larb-id = <5>;
1931 mediatek,smi = <&smi_common_vdo>;
1932 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
1933 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
1934 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;

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