mt8195.dtsi (93fbff1197474d7b65e598c6f48fa82a5c334539) mt8195.dtsi (a376a9a6491431587992e3d4319466d9adba1b58)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

--- 313 unchanged lines hidden (view full) ---

322 interrupt-controller;
323 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
324 #interrupt-cells = <2>;
325 };
326
327 watchdog: watchdog@10007000 {
328 compatible = "mediatek,mt8195-wdt",
329 "mediatek,mt6589-wdt";
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

--- 313 unchanged lines hidden (view full) ---

322 interrupt-controller;
323 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
324 #interrupt-cells = <2>;
325 };
326
327 watchdog: watchdog@10007000 {
328 compatible = "mediatek,mt8195-wdt",
329 "mediatek,mt6589-wdt";
330 mediatek,disable-extrst;
330 reg = <0 0x10007000 0 0x100>;
331 };
332
333 apmixedsys: syscon@1000c000 {
334 compatible = "mediatek,mt8195-apmixedsys", "syscon";
335 reg = <0 0x1000c000 0 0x1000>;
336 #clock-cells = <1>;
337 };

--- 760 unchanged lines hidden --- 		331 reg = <0 0x10007000 0 0x100>;
332 };
333
334 apmixedsys: syscon@1000c000 {
335 compatible = "mediatek,mt8195-apmixedsys", "syscon";
336 reg = <0 0x1000c000 0 0x1000>;
337 #clock-cells = <1>;
338 };

--- 760 unchanged lines hidden ---