mt8195.dtsi (6f84981772535e670e4e2df051a672af229b6694) mt8195.dtsi (c5fe37e8528ffb191baa7244ab33b8deaae6a4b7)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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34 device_type = "cpu";
35 compatible = "arm,cortex-a55";
36 reg = <0x000>;
37 enable-method = "psci";
38 performance-domains = <&performance 0>;
39 clock-frequency = <1701000000>;
40 capacity-dmips-mhz = <308>;
41 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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34 device_type = "cpu";
35 compatible = "arm,cortex-a55";
36 reg = <0x000>;
37 enable-method = "psci";
38 performance-domains = <&performance 0>;
39 clock-frequency = <1701000000>;
40 capacity-dmips-mhz = <308>;
41 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
42 i-cache-size = <32768>;
43 i-cache-line-size = <64>;
44 i-cache-sets = <128>;
45 d-cache-size = <32768>;
46 d-cache-line-size = <64>;
47 d-cache-sets = <128>;
42 next-level-cache = <&l2_0>;
43 #cooling-cells = <2>;
44 };
45
46 cpu1: cpu@100 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a55";
49 reg = <0x100>;
50 enable-method = "psci";
51 performance-domains = <&performance 0>;
52 clock-frequency = <1701000000>;
53 capacity-dmips-mhz = <308>;
54 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
48 next-level-cache = <&l2_0>;
49 #cooling-cells = <2>;
50 };
51
52 cpu1: cpu@100 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a55";
55 reg = <0x100>;
56 enable-method = "psci";
57 performance-domains = <&performance 0>;
58 clock-frequency = <1701000000>;
59 capacity-dmips-mhz = <308>;
60 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
61 i-cache-size = <32768>;
62 i-cache-line-size = <64>;
63 i-cache-sets = <128>;
64 d-cache-size = <32768>;
65 d-cache-line-size = <64>;
66 d-cache-sets = <128>;
55 next-level-cache = <&l2_0>;
56 #cooling-cells = <2>;
57 };
58
59 cpu2: cpu@200 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a55";
62 reg = <0x200>;
63 enable-method = "psci";
64 performance-domains = <&performance 0>;
65 clock-frequency = <1701000000>;
66 capacity-dmips-mhz = <308>;
67 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
67 next-level-cache = <&l2_0>;
68 #cooling-cells = <2>;
69 };
70
71 cpu2: cpu@200 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a55";
74 reg = <0x200>;
75 enable-method = "psci";
76 performance-domains = <&performance 0>;
77 clock-frequency = <1701000000>;
78 capacity-dmips-mhz = <308>;
79 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
80 i-cache-size = <32768>;
81 i-cache-line-size = <64>;
82 i-cache-sets = <128>;
83 d-cache-size = <32768>;
84 d-cache-line-size = <64>;
85 d-cache-sets = <128>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
70 };
71
72 cpu3: cpu@300 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a55";
75 reg = <0x300>;
76 enable-method = "psci";
77 performance-domains = <&performance 0>;
78 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
86 next-level-cache = <&l2_0>;
87 #cooling-cells = <2>;
88 };
89
90 cpu3: cpu@300 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a55";
93 reg = <0x300>;
94 enable-method = "psci";
95 performance-domains = <&performance 0>;
96 clock-frequency = <1701000000>;
97 capacity-dmips-mhz = <308>;
98 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
99 i-cache-size = <32768>;
100 i-cache-line-size = <64>;
101 i-cache-sets = <128>;
102 d-cache-size = <32768>;
103 d-cache-line-size = <64>;
104 d-cache-sets = <128>;
81 next-level-cache = <&l2_0>;
82 #cooling-cells = <2>;
83 };
84
85 cpu4: cpu@400 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a78";
88 reg = <0x400>;
89 enable-method = "psci";
90 performance-domains = <&performance 1>;
91 clock-frequency = <2171000000>;
92 capacity-dmips-mhz = <1024>;
93 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
105 next-level-cache = <&l2_0>;
106 #cooling-cells = <2>;
107 };
108
109 cpu4: cpu@400 {
110 device_type = "cpu";
111 compatible = "arm,cortex-a78";
112 reg = <0x400>;
113 enable-method = "psci";
114 performance-domains = <&performance 1>;
115 clock-frequency = <2171000000>;
116 capacity-dmips-mhz = <1024>;
117 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
118 i-cache-size = <65536>;
119 i-cache-line-size = <64>;
120 i-cache-sets = <256>;
121 d-cache-size = <65536>;
122 d-cache-line-size = <64>;
123 d-cache-sets = <256>;
94 next-level-cache = <&l2_1>;
95 #cooling-cells = <2>;
96 };
97
98 cpu5: cpu@500 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a78";
101 reg = <0x500>;
102 enable-method = "psci";
103 performance-domains = <&performance 1>;
104 clock-frequency = <2171000000>;
105 capacity-dmips-mhz = <1024>;
106 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
124 next-level-cache = <&l2_1>;
125 #cooling-cells = <2>;
126 };
127
128 cpu5: cpu@500 {
129 device_type = "cpu";
130 compatible = "arm,cortex-a78";
131 reg = <0x500>;
132 enable-method = "psci";
133 performance-domains = <&performance 1>;
134 clock-frequency = <2171000000>;
135 capacity-dmips-mhz = <1024>;
136 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
137 i-cache-size = <65536>;
138 i-cache-line-size = <64>;
139 i-cache-sets = <256>;
140 d-cache-size = <65536>;
141 d-cache-line-size = <64>;
142 d-cache-sets = <256>;
107 next-level-cache = <&l2_1>;
108 #cooling-cells = <2>;
109 };
110
111 cpu6: cpu@600 {
112 device_type = "cpu";
113 compatible = "arm,cortex-a78";
114 reg = <0x600>;
115 enable-method = "psci";
116 performance-domains = <&performance 1>;
117 clock-frequency = <2171000000>;
118 capacity-dmips-mhz = <1024>;
119 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
143 next-level-cache = <&l2_1>;
144 #cooling-cells = <2>;
145 };
146
147 cpu6: cpu@600 {
148 device_type = "cpu";
149 compatible = "arm,cortex-a78";
150 reg = <0x600>;
151 enable-method = "psci";
152 performance-domains = <&performance 1>;
153 clock-frequency = <2171000000>;
154 capacity-dmips-mhz = <1024>;
155 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
156 i-cache-size = <65536>;
157 i-cache-line-size = <64>;
158 i-cache-sets = <256>;
159 d-cache-size = <65536>;
160 d-cache-line-size = <64>;
161 d-cache-sets = <256>;
120 next-level-cache = <&l2_1>;
121 #cooling-cells = <2>;
122 };
123
124 cpu7: cpu@700 {
125 device_type = "cpu";
126 compatible = "arm,cortex-a78";
127 reg = <0x700>;
128 enable-method = "psci";
129 performance-domains = <&performance 1>;
130 clock-frequency = <2171000000>;
131 capacity-dmips-mhz = <1024>;
132 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
162 next-level-cache = <&l2_1>;
163 #cooling-cells = <2>;
164 };
165
166 cpu7: cpu@700 {
167 device_type = "cpu";
168 compatible = "arm,cortex-a78";
169 reg = <0x700>;
170 enable-method = "psci";
171 performance-domains = <&performance 1>;
172 clock-frequency = <2171000000>;
173 capacity-dmips-mhz = <1024>;
174 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
175 i-cache-size = <65536>;
176 i-cache-line-size = <64>;
177 i-cache-sets = <256>;
178 d-cache-size = <65536>;
179 d-cache-line-size = <64>;
180 d-cache-sets = <256>;
133 next-level-cache = <&l2_1>;
134 #cooling-cells = <2>;
135 };
136
137 cpu-map {
138 cluster0 {
139 core0 {
140 cpu = <&cpu0>;

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210 exit-latency-us = <200>;
211 min-residency-us = <1000>;
212 };
213 };
214
215 l2_0: l2-cache0 {
216 compatible = "cache";
217 cache-level = <2>;
181 next-level-cache = <&l2_1>;
182 #cooling-cells = <2>;
183 };
184
185 cpu-map {
186 cluster0 {
187 core0 {
188 cpu = <&cpu0>;

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258 exit-latency-us = <200>;
259 min-residency-us = <1000>;
260 };
261 };
262
263 l2_0: l2-cache0 {
264 compatible = "cache";
265 cache-level = <2>;
266 cache-size = <131072>;
267 cache-line-size = <64>;
268 cache-sets = <512>;
218 next-level-cache = <&l3_0>;
219 };
220
221 l2_1: l2-cache1 {
222 compatible = "cache";
223 cache-level = <2>;
269 next-level-cache = <&l3_0>;
270 };
271
272 l2_1: l2-cache1 {
273 compatible = "cache";
274 cache-level = <2>;
275 cache-size = <262144>;
276 cache-line-size = <64>;
277 cache-sets = <512>;
224 next-level-cache = <&l3_0>;
225 };
226
227 l3_0: l3-cache {
228 compatible = "cache";
229 cache-level = <3>;
278 next-level-cache = <&l3_0>;
279 };
280
281 l3_0: l3-cache {
282 compatible = "cache";
283 cache-level = <3>;
284 cache-size = <2097152>;
285 cache-line-size = <64>;
286 cache-sets = <2048>;
287 cache-unified;
230 };
231 };
232
233 dsu-pmu {
234 compatible = "arm,dsu-pmu";
235 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
236 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
237 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;

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243 wakeup-delay-ms = <50>;
244 };
245
246 sound: mt8195-sound {
247 mediatek,platform = <&afe>;
248 status = "disabled";
249 };
250
288 };
289 };
290
291 dsu-pmu {
292 compatible = "arm,dsu-pmu";
293 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
294 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
295 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;

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301 wakeup-delay-ms = <50>;
302 };
303
304 sound: mt8195-sound {
305 mediatek,platform = <&afe>;
306 status = "disabled";
307 };
308
309 clk13m: fixed-factor-clock-13m {
310 compatible = "fixed-factor-clock";
311 #clock-cells = <0>;
312 clocks = <&clk26m>;
313 clock-div = <2>;
314 clock-mult = <1>;
315 clock-output-names = "clk13m";
316 };
317
251 clk26m: oscillator-26m {
252 compatible = "fixed-clock";
253 #clock-cells = <0>;
254 clock-frequency = <26000000>;
255 clock-output-names = "clk26m";
256 };
257
258 clk32k: oscillator-32k {

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700 #clock-cells = <1>;
701 };
702
703 systimer: timer@10017000 {
704 compatible = "mediatek,mt8195-timer",
705 "mediatek,mt6765-timer";
706 reg = <0 0x10017000 0 0x1000>;
707 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
318 clk26m: oscillator-26m {
319 compatible = "fixed-clock";
320 #clock-cells = <0>;
321 clock-frequency = <26000000>;
322 clock-output-names = "clk26m";
323 };
324
325 clk32k: oscillator-32k {

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767 #clock-cells = <1>;
768 };
769
770 systimer: timer@10017000 {
771 compatible = "mediatek,mt8195-timer",
772 "mediatek,mt6765-timer";
773 reg = <0 0x10017000 0 0x1000>;
774 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
708 clocks = <&topckgen CLK_TOP_CLK26M_D2>;
775 clocks = <&clk13m>;
709 };
710
711 pwrap: pwrap@10024000 {
712 compatible = "mediatek,mt8195-pwrap", "syscon";
713 reg = <0 0x10024000 0 0x1000>;
714 reg-names = "pwrap";
715 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
716 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,

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1041 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1042 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1043 clock-names = "spi";
1044 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1045 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1046 status = "disabled";
1047 };
1048
776 };
777
778 pwrap: pwrap@10024000 {
779 compatible = "mediatek,mt8195-pwrap", "syscon";
780 reg = <0 0x10024000 0 0x1000>;
781 reg-names = "pwrap";
782 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
783 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,

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1108 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1109 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1110 clock-names = "spi";
1111 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1112 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1113 status = "disabled";
1114 };
1115
1116 eth: ethernet@11021000 {
1117 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1118 reg = <0 0x11021000 0 0x4000>;
1119 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
1120 interrupt-names = "macirq";
1121 clock-names = "axi",
1122 "apb",
1123 "mac_main",
1124 "ptp_ref",
1125 "rmii_internal",
1126 "mac_cg";
1127 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
1128 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
1129 <&topckgen CLK_TOP_SNPS_ETH_250M>,
1130 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1131 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1132 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
1133 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1134 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1135 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
1136 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1137 <&topckgen CLK_TOP_ETHPLL_D8>,
1138 <&topckgen CLK_TOP_ETHPLL_D10>;
1139 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1140 mediatek,pericfg = <&infracfg_ao>;
1141 snps,axi-config = <&stmmac_axi_setup>;
1142 snps,mtl-rx-config = <&mtl_rx_setup>;
1143 snps,mtl-tx-config = <&mtl_tx_setup>;
1144 snps,txpbl = <16>;
1145 snps,rxpbl = <16>;
1146 snps,clk-csr = <0>;
1147 status = "disabled";
1148
1149 mdio {
1150 compatible = "snps,dwmac-mdio";
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1153 };
1154
1155 stmmac_axi_setup: stmmac-axi-config {
1156 snps,wr_osr_lmt = <0x7>;
1157 snps,rd_osr_lmt = <0x7>;
1158 snps,blen = <0 0 0 0 16 8 4>;
1159 };
1160
1161 mtl_rx_setup: rx-queues-config {
1162 snps,rx-queues-to-use = <4>;
1163 snps,rx-sched-sp;
1164 queue0 {
1165 snps,dcb-algorithm;
1166 snps,map-to-dma-channel = <0x0>;
1167 };
1168 queue1 {
1169 snps,dcb-algorithm;
1170 snps,map-to-dma-channel = <0x0>;
1171 };
1172 queue2 {
1173 snps,dcb-algorithm;
1174 snps,map-to-dma-channel = <0x0>;
1175 };
1176 queue3 {
1177 snps,dcb-algorithm;
1178 snps,map-to-dma-channel = <0x0>;
1179 };
1180 };
1181
1182 mtl_tx_setup: tx-queues-config {
1183 snps,tx-queues-to-use = <4>;
1184 snps,tx-sched-wrr;
1185 queue0 {
1186 snps,weight = <0x10>;
1187 snps,dcb-algorithm;
1188 snps,priority = <0x0>;
1189 };
1190 queue1 {
1191 snps,weight = <0x11>;
1192 snps,dcb-algorithm;
1193 snps,priority = <0x1>;
1194 };
1195 queue2 {
1196 snps,weight = <0x12>;
1197 snps,dcb-algorithm;
1198 snps,priority = <0x2>;
1199 };
1200 queue3 {
1201 snps,weight = <0x13>;
1202 snps,dcb-algorithm;
1203 snps,priority = <0x3>;
1204 };
1205 };
1206 };
1207
1049 xhci0: usb@11200000 {
1050 compatible = "mediatek,mt8195-xhci",
1051 "mediatek,mtk-xhci";
1052 reg = <0 0x11200000 0 0x1000>,
1053 <0 0x11203e00 0 0x0100>;
1054 reg-names = "mac", "ippc";
1055 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1056 phys = <&u2port0 PHY_TYPE_USB2>,

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1253 <0x82000000 0 0x24200000
1254 0x0 0x24200000 0 0x3e00000>;
1255
1256 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1257 iommu-map-mask = <0x0>;
1258
1259 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
1260 <&clk26m>,
1208 xhci0: usb@11200000 {
1209 compatible = "mediatek,mt8195-xhci",
1210 "mediatek,mtk-xhci";
1211 reg = <0 0x11200000 0 0x1000>,
1212 <0 0x11203e00 0 0x0100>;
1213 reg-names = "mac", "ippc";
1214 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1215 phys = <&u2port0 PHY_TYPE_USB2>,

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1412 <0x82000000 0 0x24200000
1413 0x0 0x24200000 0 0x3e00000>;
1414
1415 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1416 iommu-map-mask = <0x0>;
1417
1418 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
1419 <&clk26m>,
1261 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
1420 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>,
1262 <&clk26m>,
1421 <&clk26m>,
1263 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
1422 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>,
1264 /* Designer has connect pcie1 with peri_mem_p0 clock */
1265 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1266 clock-names = "pl_250m", "tl_26m", "tl_96m",
1267 "tl_32k", "peri_26m", "peri_mem";
1268 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1269 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1270
1271 phys = <&u3port1 PHY_TYPE_PCIE>;

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1544 #clock-cells = <1>;
1545 };
1546
1547 u3phy1: t-phy@11e30000 {
1548 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1549 #address-cells = <1>;
1550 #size-cells = <1>;
1551 ranges = <0 0 0x11e30000 0xe00>;
1423 /* Designer has connect pcie1 with peri_mem_p0 clock */
1424 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1425 clock-names = "pl_250m", "tl_26m", "tl_96m",
1426 "tl_32k", "peri_26m", "peri_mem";
1427 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1428 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1429
1430 phys = <&u3port1 PHY_TYPE_PCIE>;

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1703 #clock-cells = <1>;
1704 };
1705
1706 u3phy1: t-phy@11e30000 {
1707 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1708 #address-cells = <1>;
1709 #size-cells = <1>;
1710 ranges = <0 0 0x11e30000 0xe00>;
1711 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1552 status = "disabled";
1553
1554 u2port1: usb-phy@0 {
1555 reg = <0x0 0x700>;
1556 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1557 <&clk26m>;
1558 clock-names = "ref", "da_ref";
1559 #phy-cells = <1>;

--- 825 unchanged lines hidden --- 		1712 status = "disabled";
1713
1714 u2port1: usb-phy@0 {
1715 reg = <0x0 0x700>;
1716 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1717 <&clk26m>;
1718 clock-names = "ref", "da_ref";
1719 #phy-cells = <1>;

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