mt8195.dtsi (6c2503b5856aa5fbeb7f9147400dd7d6988b9373) mt8195.dtsi (64196979f91832b7b7bae1fb60f7998b7b88935f)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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1372 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1373 reg = <0x192 0x1>;
1374 bits = <4 4>;
1375 };
1376 pciephy_glb_intr: pciephy-glb-intr@193 {
1377 reg = <0x193 0x1>;
1378 bits = <0 4>;
1379 };
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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1372 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1373 reg = <0x192 0x1>;
1374 bits = <4 4>;
1375 };
1376 pciephy_glb_intr: pciephy-glb-intr@193 {
1377 reg = <0x193 0x1>;
1378 bits = <0 4>;
1379 };
1380 dp_calibration: dp-data@1ac {
1381 reg = <0x1ac 0x10>;
1382 };
1380 };
1381
1382 u3phy2: t-phy@11c40000 {
1383 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1384 #address-cells = <1>;
1385 #size-cells = <1>;
1386 ranges = <0 0 0x11c40000 0x700>;
1387 status = "disabled";

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2350 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
2351 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2352 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
2353 <&vdosys1 CLK_VDO1_DPINTF>,
2354 <&apmixedsys CLK_APMIXED_TVDPLL2>;
2355 clock-names = "engine", "pixel", "pll";
2356 status = "disabled";
2357 };
1383 };
1384
1385 u3phy2: t-phy@11c40000 {
1386 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1387 #address-cells = <1>;
1388 #size-cells = <1>;
1389 ranges = <0 0 0x11c40000 0x700>;
1390 status = "disabled";

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2353 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
2354 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2355 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
2356 <&vdosys1 CLK_VDO1_DPINTF>,
2357 <&apmixedsys CLK_APMIXED_TVDPLL2>;
2358 clock-names = "engine", "pixel", "pll";
2359 status = "disabled";
2360 };
2361
2362 edp_tx: edp-tx@1c500000 {
2363 compatible = "mediatek,mt8195-edp-tx";
2364 reg = <0 0x1c500000 0 0x8000>;
2365 nvmem-cells = <&dp_calibration>;
2366 nvmem-cell-names = "dp_calibration_data";
2367 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
2368 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
2369 max-linkrate-mhz = <8100>;
2370 status = "disabled";
2371 };
2372
2373 dp_tx: dp-tx@1c600000 {
2374 compatible = "mediatek,mt8195-dp-tx";
2375 reg = <0 0x1c600000 0 0x8000>;
2376 nvmem-cells = <&dp_calibration>;
2377 nvmem-cell-names = "dp_calibration_data";
2378 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
2379 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
2380 max-linkrate-mhz = <8100>;
2381 status = "disabled";
2382 };
2358 };
2359};
2383 };
2384};