mt8195.dtsi (67a1723344cfe05430977483d6d3c7a999480143) mt8195.dtsi (3106b14c1cb4b745dd0413dc392418d301f3b1d1)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

--- 524 unchanged lines hidden (view full) ---

533
534 /* power domain of the SoC */
535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
536 reg = <MT8195_POWER_DOMAIN_MFG0>;
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <1>;
540
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

--- 524 unchanged lines hidden (view full) ---

533
534 /* power domain of the SoC */
535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
536 reg = <MT8195_POWER_DOMAIN_MFG0>;
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <1>;
540
541 power-domain@MT8195_POWER_DOMAIN_MFG1 {
541 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 {
542 reg = <MT8195_POWER_DOMAIN_MFG1>;
543 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
544 <&topckgen CLK_TOP_MFG_CORE_TMP>;
545 clock-names = "mfg", "alt";
546 mediatek,infracfg = <&infracfg_ao>;
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #power-domain-cells = <1>;

--- 72 unchanged lines hidden (view full) ---

622 clocks = <&vdecsys CLK_VDEC_LARB1>;
623 clock-names = "vdec1-0";
624 mediatek,infracfg = <&infracfg_ao>;
625 #power-domain-cells = <0>;
626 };
627
628 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
629 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
542 reg = <MT8195_POWER_DOMAIN_MFG1>;
543 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
544 <&topckgen CLK_TOP_MFG_CORE_TMP>;
545 clock-names = "mfg", "alt";
546 mediatek,infracfg = <&infracfg_ao>;
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #power-domain-cells = <1>;

--- 72 unchanged lines hidden (view full) ---

622 clocks = <&vdecsys CLK_VDEC_LARB1>;
623 clock-names = "vdec1-0";
624 mediatek,infracfg = <&infracfg_ao>;
625 #power-domain-cells = <0>;
626 };
627
628 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
629 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
630 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
631 clock-names = "venc1-larb";
632 mediatek,infracfg = <&infracfg_ao>;
633 #power-domain-cells = <0>;
634 };
635
636 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
637 reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
638 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
639 <&vdosys0 CLK_VDO0_SMI_GALS>,

--- 46 unchanged lines hidden (view full) ---

686 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
687 clock-names = "vdec2-0";
688 mediatek,infracfg = <&infracfg_ao>;
689 #power-domain-cells = <0>;
690 };
691
692 power-domain@MT8195_POWER_DOMAIN_VENC {
693 reg = <MT8195_POWER_DOMAIN_VENC>;
630 mediatek,infracfg = <&infracfg_ao>;
631 #power-domain-cells = <0>;
632 };
633
634 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
635 reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
636 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
637 <&vdosys0 CLK_VDO0_SMI_GALS>,

--- 46 unchanged lines hidden (view full) ---

684 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
685 clock-names = "vdec2-0";
686 mediatek,infracfg = <&infracfg_ao>;
687 #power-domain-cells = <0>;
688 };
689
690 power-domain@MT8195_POWER_DOMAIN_VENC {
691 reg = <MT8195_POWER_DOMAIN_VENC>;
694 clocks = <&vencsys CLK_VENC_LARB>;
695 clock-names = "venc0-larb";
696 mediatek,infracfg = <&infracfg_ao>;
697 #power-domain-cells = <0>;
698 };
699
700 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
701 reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
702 clocks = <&topckgen CLK_TOP_CFG_VDO1>,
703 <&vdosys1 CLK_VDO1_SMI_LARB2>,

--- 1960 unchanged lines hidden (view full) ---

2664 };
2665 };
2666
2667 larb20: larb@1b010000 {
2668 compatible = "mediatek,mt8195-smi-larb";
2669 reg = <0 0x1b010000 0 0x1000>;
2670 mediatek,larb-id = <20>;
2671 mediatek,smi = <&smi_common_vpp>;
692 mediatek,infracfg = <&infracfg_ao>;
693 #power-domain-cells = <0>;
694 };
695
696 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
697 reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
698 clocks = <&topckgen CLK_TOP_CFG_VDO1>,
699 <&vdosys1 CLK_VDO1_SMI_LARB2>,

--- 1960 unchanged lines hidden (view full) ---

2660 };
2661 };
2662
2663 larb20: larb@1b010000 {
2664 compatible = "mediatek,mt8195-smi-larb";
2665 reg = <0 0x1b010000 0 0x1000>;
2666 mediatek,larb-id = <20>;
2667 mediatek,smi = <&smi_common_vpp>;
2672 clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>,
2668 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
2673 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
2674 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
2675 clock-names = "apb", "smi", "gals";
2676 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2677 };
2678
2679 ovl0: ovl@1c000000 {
2680 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";

--- 845 unchanged lines hidden --- 		2669 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
2670 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
2671 clock-names = "apb", "smi", "gals";
2672 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2673 };
2674
2675 ovl0: ovl@1c000000 {
2676 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";

--- 845 unchanged lines hidden ---