mt8195.dtsi (513c43328b189874fdfee3ae99cac81e5502e7f7) mt8195.dtsi (6c2503b5856aa5fbeb7f9147400dd7d6988b9373)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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2239 compatible = "mediatek,mt8195-disp-merge";
2240 reg = <0 0x1c014000 0 0x1000>;
2241 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
2242 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2243 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
2244 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
2245 };
2246
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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2239 compatible = "mediatek,mt8195-disp-merge";
2240 reg = <0 0x1c014000 0 0x1000>;
2241 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
2242 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2243 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
2244 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
2245 };
2246
2247 dp_intf0: dp-intf@1c015000 {
2248 compatible = "mediatek,mt8195-dp-intf";
2249 reg = <0 0x1c015000 0 0x1000>;
2250 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
2251 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
2252 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
2253 <&apmixedsys CLK_APMIXED_TVDPLL1>;
2254 clock-names = "engine", "pixel", "pll";
2255 status = "disabled";
2256 };
2257
2247 mutex: mutex@1c016000 {
2248 compatible = "mediatek,mt8195-disp-mutex";
2249 reg = <0 0x1c016000 0 0x1000>;
2250 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
2251 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2252 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
2253 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
2254 };

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2327 mediatek,larb-id = <3>;
2328 mediatek,smi = <&smi_common_vpp>;
2329 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
2330 <&vdosys1 CLK_VDO1_GALS>,
2331 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
2332 clock-names = "apb", "smi", "gals";
2333 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2334 };
2258 mutex: mutex@1c016000 {
2259 compatible = "mediatek,mt8195-disp-mutex";
2260 reg = <0 0x1c016000 0 0x1000>;
2261 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
2262 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2263 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
2264 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
2265 };

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2338 mediatek,larb-id = <3>;
2339 mediatek,smi = <&smi_common_vpp>;
2340 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
2341 <&vdosys1 CLK_VDO1_GALS>,
2342 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
2343 clock-names = "apb", "smi", "gals";
2344 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2345 };
2346
2347 dp_intf1: dp-intf@1c113000 {
2348 compatible = "mediatek,mt8195-dp-intf";
2349 reg = <0 0x1c113000 0 0x1000>;
2350 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
2351 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2352 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
2353 <&vdosys1 CLK_VDO1_DPINTF>,
2354 <&apmixedsys CLK_APMIXED_TVDPLL2>;
2355 clock-names = "engine", "pixel", "pll";
2356 status = "disabled";
2357 };
2335 };
2336};
2358 };
2359};