mt8195.dtsi (4436e6da008fee87d54c038e983e5be9a6baf8fb) mt8195.dtsi (51bc68debab9e30b50c6352315950f3cfc309b32)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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1439
1440 xhci1: usb@11290000 {
1441 compatible = "mediatek,mt8195-xhci",
1442 "mediatek,mtk-xhci";
1443 reg = <0 0x11290000 0 0x1000>,
1444 <0 0x11293e00 0 0x0100>;
1445 reg-names = "mac", "ippc";
1446 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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1439
1440 xhci1: usb@11290000 {
1441 compatible = "mediatek,mt8195-xhci",
1442 "mediatek,mtk-xhci";
1443 reg = <0 0x11290000 0 0x1000>,
1444 <0 0x11293e00 0 0x0100>;
1445 reg-names = "mac", "ippc";
1446 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
1447 phys = <&u2port1 PHY_TYPE_USB2>;
1447 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
1448 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1449 <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1450 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1451 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1452 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
1453 <&topckgen CLK_TOP_SSUSB_P1_REF>,
1454 <&apmixedsys CLK_APMIXED_USB1PLL>,
1455 <&clk26m>,

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2032 };
2033
2034 dma-controller@14001000 {
2035 compatible = "mediatek,mt8195-mdp3-rdma";
2036 reg = <0 0x14001000 0 0x1000>;
2037 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2038 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2039 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
1448 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1449 <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1450 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1451 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1452 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
1453 <&topckgen CLK_TOP_SSUSB_P1_REF>,
1454 <&apmixedsys CLK_APMIXED_USB1PLL>,
1455 <&clk26m>,

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2032 };
2033
2034 dma-controller@14001000 {
2035 compatible = "mediatek,mt8195-mdp3-rdma";
2036 reg = <0 0x14001000 0 0x1000>;
2037 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2038 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2039 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
2040 mediatek,scp = <&scp>;
2040 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2041 iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>;
2042 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
2043 mboxes = <&gce1 12 CMDQ_THR_PRIO_1>,
2044 <&gce1 13 CMDQ_THR_PRIO_1>,
2045 <&gce1 14 CMDQ_THR_PRIO_1>,
2046 <&gce1 21 CMDQ_THR_PRIO_1>,
2047 <&gce1 22 CMDQ_THR_PRIO_1>;

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3246 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
3247 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3248 };
3249
3250 dp_intf0: dp-intf@1c015000 {
3251 compatible = "mediatek,mt8195-dp-intf";
3252 reg = <0 0x1c015000 0 0x1000>;
3253 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
2041 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2042 iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>;
2043 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
2044 mboxes = <&gce1 12 CMDQ_THR_PRIO_1>,
2045 <&gce1 13 CMDQ_THR_PRIO_1>,
2046 <&gce1 14 CMDQ_THR_PRIO_1>,
2047 <&gce1 21 CMDQ_THR_PRIO_1>,
2048 <&gce1 22 CMDQ_THR_PRIO_1>;

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3247 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
3248 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3249 };
3250
3251 dp_intf0: dp-intf@1c015000 {
3252 compatible = "mediatek,mt8195-dp-intf";
3253 reg = <0 0x1c015000 0 0x1000>;
3254 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
3254 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
3255 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
3255 clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
3256 <&vdosys0 CLK_VDO0_DP_INTF0>,
3256 <&apmixedsys CLK_APMIXED_TVDPLL1>;
3257 <&apmixedsys CLK_APMIXED_TVDPLL1>;
3257 clock-names = "engine", "pixel", "pll";
3258 clock-names = "pixel", "engine", "pll";
3258 status = "disabled";
3259 };
3260
3261 mutex: mutex@1c016000 {
3262 compatible = "mediatek,mt8195-disp-mutex";
3263 reg = <0 0x1c016000 0 0x1000>;
3264 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
3265 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;

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3516 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
3517 };
3518
3519 dp_intf1: dp-intf@1c113000 {
3520 compatible = "mediatek,mt8195-dp-intf";
3521 reg = <0 0x1c113000 0 0x1000>;
3522 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
3523 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3259 status = "disabled";
3260 };
3261
3262 mutex: mutex@1c016000 {
3263 compatible = "mediatek,mt8195-disp-mutex";
3264 reg = <0 0x1c016000 0 0x1000>;
3265 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
3266 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;

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3517 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
3518 };
3519
3520 dp_intf1: dp-intf@1c113000 {
3521 compatible = "mediatek,mt8195-dp-intf";
3522 reg = <0 0x1c113000 0 0x1000>;
3523 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
3524 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3524 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
3525 <&vdosys1 CLK_VDO1_DPINTF>,
3525 clocks = <&vdosys1 CLK_VDO1_DPINTF>,
3526 <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
3526 <&apmixedsys CLK_APMIXED_TVDPLL2>;
3527 <&apmixedsys CLK_APMIXED_TVDPLL2>;
3527 clock-names = "engine", "pixel", "pll";
3528 clock-names = "pixel", "engine", "pll";
3528 status = "disabled";
3529 };
3530
3531 ethdr0: hdr-engine@1c114000 {
3532 compatible = "mediatek,mt8195-disp-ethdr";
3533 reg = <0 0x1c114000 0 0x1000>,
3534 <0 0x1c115000 0 0x1000>,
3535 <0 0x1c117000 0 0x1000>,

--- 488 unchanged lines hidden --- 		3529 status = "disabled";
3530 };
3531
3532 ethdr0: hdr-engine@1c114000 {
3533 compatible = "mediatek,mt8195-disp-ethdr";
3534 reg = <0 0x1c114000 0 0x1000>,
3535 <0 0x1c115000 0 0x1000>,
3536 <0 0x1c117000 0 0x1000>,

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