mt8195.dtsi (3b129949184a1251e6a42db714f6d68b75fabedd) mt8195.dtsi (58f126296c3c52d02bf3fad1f68c331d718c4a9b)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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3330 mutex1: mutex@1c101000 {
3331 compatible = "mediatek,mt8195-disp-mutex";
3332 reg = <0 0x1c101000 0 0x1000>;
3333 reg-names = "vdo1_mutex";
3334 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
3335 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3336 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
3337 clock-names = "vdo1_mutex";
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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3330 mutex1: mutex@1c101000 {
3331 compatible = "mediatek,mt8195-disp-mutex";
3332 reg = <0 0x1c101000 0 0x1000>;
3333 reg-names = "vdo1_mutex";
3334 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
3335 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3336 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
3337 clock-names = "vdo1_mutex";
3338 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
3338 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3339 };
3340
3341 larb2: larb@1c102000 {
3342 compatible = "mediatek,mt8195-smi-larb";
3343 reg = <0 0x1c102000 0 0x1000>;
3344 mediatek,larb-id = <2>;
3345 mediatek,smi = <&smi_common_vdo>;

--- 677 unchanged lines hidden --- 		3339 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3340 };
3341
3342 larb2: larb@1c102000 {
3343 compatible = "mediatek,mt8195-smi-larb";
3344 reg = <0 0x1c102000 0 0x1000>;
3345 mediatek,larb-id = <2>;
3346 mediatek,smi = <&smi_common_vdo>;

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