mt8195.dtsi (3106b14c1cb4b745dd0413dc392418d301f3b1d1) mt8195.dtsi (52f4a10f2a860402c130c5c21d055e721d63a7e9)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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2864 mediatek,smi = <&smi_common_vpp>;
2865 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
2866 <&vdosys1 CLK_VDO1_GALS>,
2867 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
2868 clock-names = "apb", "smi", "gals";
2869 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2870 };
2871
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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2864 mediatek,smi = <&smi_common_vpp>;
2865 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
2866 <&vdosys1 CLK_VDO1_GALS>,
2867 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
2868 clock-names = "apb", "smi", "gals";
2869 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2870 };
2871
2872 vdo1_rdma0: rdma@1c104000 {
2872 vdo1_rdma0: dma-controller@1c104000 {
2873 compatible = "mediatek,mt8195-vdo1-rdma";
2874 reg = <0 0x1c104000 0 0x1000>;
2875 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
2876 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
2877 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2878 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
2879 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
2873 compatible = "mediatek,mt8195-vdo1-rdma";
2874 reg = <0 0x1c104000 0 0x1000>;
2875 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
2876 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
2877 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2878 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
2879 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
2880 #dma-cells = <1>;
2880 };
2881
2881 };
2882
2882 vdo1_rdma1: rdma@1c105000 {
2883 vdo1_rdma1: dma-controller@1c105000 {
2883 compatible = "mediatek,mt8195-vdo1-rdma";
2884 reg = <0 0x1c105000 0 0x1000>;
2885 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
2886 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
2887 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2888 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
2889 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
2884 compatible = "mediatek,mt8195-vdo1-rdma";
2885 reg = <0 0x1c105000 0 0x1000>;
2886 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
2887 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
2888 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2889 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
2890 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
2891 #dma-cells = <1>;
2890 };
2891
2892 };
2893
2892 vdo1_rdma2: rdma@1c106000 {
2894 vdo1_rdma2: dma-controller@1c106000 {
2893 compatible = "mediatek,mt8195-vdo1-rdma";
2894 reg = <0 0x1c106000 0 0x1000>;
2895 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
2896 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
2897 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2898 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
2899 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
2895 compatible = "mediatek,mt8195-vdo1-rdma";
2896 reg = <0 0x1c106000 0 0x1000>;
2897 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
2898 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
2899 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2900 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
2901 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
2902 #dma-cells = <1>;
2900 };
2901
2903 };
2904
2902 vdo1_rdma3: rdma@1c107000 {
2905 vdo1_rdma3: dma-controller@1c107000 {
2903 compatible = "mediatek,mt8195-vdo1-rdma";
2904 reg = <0 0x1c107000 0 0x1000>;
2905 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
2906 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
2907 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2908 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
2909 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
2906 compatible = "mediatek,mt8195-vdo1-rdma";
2907 reg = <0 0x1c107000 0 0x1000>;
2908 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
2909 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
2910 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2911 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
2912 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
2913 #dma-cells = <1>;
2910 };
2911
2914 };
2915
2912 vdo1_rdma4: rdma@1c108000 {
2916 vdo1_rdma4: dma-controller@1c108000 {
2913 compatible = "mediatek,mt8195-vdo1-rdma";
2914 reg = <0 0x1c108000 0 0x1000>;
2915 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
2916 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
2917 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2918 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
2919 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
2917 compatible = "mediatek,mt8195-vdo1-rdma";
2918 reg = <0 0x1c108000 0 0x1000>;
2919 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
2920 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
2921 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2922 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
2923 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
2924 #dma-cells = <1>;
2920 };
2921
2925 };
2926
2922 vdo1_rdma5: rdma@1c109000 {
2927 vdo1_rdma5: dma-controller@1c109000 {
2923 compatible = "mediatek,mt8195-vdo1-rdma";
2924 reg = <0 0x1c109000 0 0x1000>;
2925 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
2926 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
2927 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2928 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
2929 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
2928 compatible = "mediatek,mt8195-vdo1-rdma";
2929 reg = <0 0x1c109000 0 0x1000>;
2930 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
2931 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
2932 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2933 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
2934 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
2935 #dma-cells = <1>;
2930 };
2931
2936 };
2937
2932 vdo1_rdma6: rdma@1c10a000 {
2938 vdo1_rdma6: dma-controller@1c10a000 {
2933 compatible = "mediatek,mt8195-vdo1-rdma";
2934 reg = <0 0x1c10a000 0 0x1000>;
2935 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
2936 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
2937 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2938 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
2939 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
2939 compatible = "mediatek,mt8195-vdo1-rdma";
2940 reg = <0 0x1c10a000 0 0x1000>;
2941 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
2942 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
2943 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2944 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
2945 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
2946 #dma-cells = <1>;
2940 };
2941
2947 };
2948
2942 vdo1_rdma7: rdma@1c10b000 {
2949 vdo1_rdma7: dma-controller@1c10b000 {
2943 compatible = "mediatek,mt8195-vdo1-rdma";
2944 reg = <0 0x1c10b000 0 0x1000>;
2945 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
2946 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
2947 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2948 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
2949 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
2950 compatible = "mediatek,mt8195-vdo1-rdma";
2951 reg = <0 0x1c10b000 0 0x1000>;
2952 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
2953 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
2954 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2955 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
2956 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
2957 #dma-cells = <1>;
2950 };
2951
2952 merge1: vpp-merge@1c10c000 {
2953 compatible = "mediatek,mt8195-disp-merge";
2954 reg = <0 0x1c10c000 0 0x1000>;
2955 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
2956 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
2957 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;

--- 564 unchanged lines hidden --- 		2958 };
2959
2960 merge1: vpp-merge@1c10c000 {
2961 compatible = "mediatek,mt8195-disp-merge";
2962 reg = <0 0x1c10c000 0 0x1000>;
2963 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
2964 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
2965 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;

--- 564 unchanged lines hidden ---