mt8195.dtsi (26ed1d29fc44f3f2f0c396c1392abefac5f0454e) mt8195.dtsi (981f808e641c624fdf4ece806b599ae66e875ee4)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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33 cpu0: cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a55";
36 reg = <0x000>;
37 enable-method = "psci";
38 performance-domains = <&performance 0>;
39 clock-frequency = <1701000000>;
40 capacity-dmips-mhz = <308>;
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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33 cpu0: cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a55";
36 reg = <0x000>;
37 enable-method = "psci";
38 performance-domains = <&performance 0>;
39 clock-frequency = <1701000000>;
40 capacity-dmips-mhz = <308>;
41 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
41 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
42 i-cache-size = <32768>;
43 i-cache-line-size = <64>;
44 i-cache-sets = <128>;
45 d-cache-size = <32768>;
46 d-cache-line-size = <64>;
47 d-cache-sets = <128>;
42 next-level-cache = <&l2_0>;
43 #cooling-cells = <2>;
44 };
45
46 cpu1: cpu@100 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a55";
49 reg = <0x100>;
50 enable-method = "psci";
51 performance-domains = <&performance 0>;
52 clock-frequency = <1701000000>;
53 capacity-dmips-mhz = <308>;
48 next-level-cache = <&l2_0>;
49 #cooling-cells = <2>;
50 };
51
52 cpu1: cpu@100 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a55";
55 reg = <0x100>;
56 enable-method = "psci";
57 performance-domains = <&performance 0>;
58 clock-frequency = <1701000000>;
59 capacity-dmips-mhz = <308>;
54 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
60 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
61 i-cache-size = <32768>;
62 i-cache-line-size = <64>;
63 i-cache-sets = <128>;
64 d-cache-size = <32768>;
65 d-cache-line-size = <64>;
66 d-cache-sets = <128>;
55 next-level-cache = <&l2_0>;
56 #cooling-cells = <2>;
57 };
58
59 cpu2: cpu@200 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a55";
62 reg = <0x200>;
63 enable-method = "psci";
64 performance-domains = <&performance 0>;
65 clock-frequency = <1701000000>;
66 capacity-dmips-mhz = <308>;
67 next-level-cache = <&l2_0>;
68 #cooling-cells = <2>;
69 };
70
71 cpu2: cpu@200 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a55";
74 reg = <0x200>;
75 enable-method = "psci";
76 performance-domains = <&performance 0>;
77 clock-frequency = <1701000000>;
78 capacity-dmips-mhz = <308>;
67 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
79 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
80 i-cache-size = <32768>;
81 i-cache-line-size = <64>;
82 i-cache-sets = <128>;
83 d-cache-size = <32768>;
84 d-cache-line-size = <64>;
85 d-cache-sets = <128>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
70 };
71
72 cpu3: cpu@300 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a55";
75 reg = <0x300>;
76 enable-method = "psci";
77 performance-domains = <&performance 0>;
78 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = <308>;
86 next-level-cache = <&l2_0>;
87 #cooling-cells = <2>;
88 };
89
90 cpu3: cpu@300 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a55";
93 reg = <0x300>;
94 enable-method = "psci";
95 performance-domains = <&performance 0>;
96 clock-frequency = <1701000000>;
97 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
98 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
99 i-cache-size = <32768>;
100 i-cache-line-size = <64>;
101 i-cache-sets = <128>;
102 d-cache-size = <32768>;
103 d-cache-line-size = <64>;
104 d-cache-sets = <128>;
81 next-level-cache = <&l2_0>;
82 #cooling-cells = <2>;
83 };
84
85 cpu4: cpu@400 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a78";
88 reg = <0x400>;
89 enable-method = "psci";
90 performance-domains = <&performance 1>;
91 clock-frequency = <2171000000>;
92 capacity-dmips-mhz = <1024>;
105 next-level-cache = <&l2_0>;
106 #cooling-cells = <2>;
107 };
108
109 cpu4: cpu@400 {
110 device_type = "cpu";
111 compatible = "arm,cortex-a78";
112 reg = <0x400>;
113 enable-method = "psci";
114 performance-domains = <&performance 1>;
115 clock-frequency = <2171000000>;
116 capacity-dmips-mhz = <1024>;
93 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
117 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
118 i-cache-size = <65536>;
119 i-cache-line-size = <64>;
120 i-cache-sets = <256>;
121 d-cache-size = <65536>;
122 d-cache-line-size = <64>;
123 d-cache-sets = <256>;
94 next-level-cache = <&l2_1>;
95 #cooling-cells = <2>;
96 };
97
98 cpu5: cpu@500 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a78";
101 reg = <0x500>;
102 enable-method = "psci";
103 performance-domains = <&performance 1>;
104 clock-frequency = <2171000000>;
105 capacity-dmips-mhz = <1024>;
124 next-level-cache = <&l2_1>;
125 #cooling-cells = <2>;
126 };
127
128 cpu5: cpu@500 {
129 device_type = "cpu";
130 compatible = "arm,cortex-a78";
131 reg = <0x500>;
132 enable-method = "psci";
133 performance-domains = <&performance 1>;
134 clock-frequency = <2171000000>;
135 capacity-dmips-mhz = <1024>;
106 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
136 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
137 i-cache-size = <65536>;
138 i-cache-line-size = <64>;
139 i-cache-sets = <256>;
140 d-cache-size = <65536>;
141 d-cache-line-size = <64>;
142 d-cache-sets = <256>;
107 next-level-cache = <&l2_1>;
108 #cooling-cells = <2>;
109 };
110
111 cpu6: cpu@600 {
112 device_type = "cpu";
113 compatible = "arm,cortex-a78";
114 reg = <0x600>;
115 enable-method = "psci";
116 performance-domains = <&performance 1>;
117 clock-frequency = <2171000000>;
118 capacity-dmips-mhz = <1024>;
143 next-level-cache = <&l2_1>;
144 #cooling-cells = <2>;
145 };
146
147 cpu6: cpu@600 {
148 device_type = "cpu";
149 compatible = "arm,cortex-a78";
150 reg = <0x600>;
151 enable-method = "psci";
152 performance-domains = <&performance 1>;
153 clock-frequency = <2171000000>;
154 capacity-dmips-mhz = <1024>;
119 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
155 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
156 i-cache-size = <65536>;
157 i-cache-line-size = <64>;
158 i-cache-sets = <256>;
159 d-cache-size = <65536>;
160 d-cache-line-size = <64>;
161 d-cache-sets = <256>;
120 next-level-cache = <&l2_1>;
121 #cooling-cells = <2>;
122 };
123
124 cpu7: cpu@700 {
125 device_type = "cpu";
126 compatible = "arm,cortex-a78";
127 reg = <0x700>;
128 enable-method = "psci";
129 performance-domains = <&performance 1>;
130 clock-frequency = <2171000000>;
131 capacity-dmips-mhz = <1024>;
162 next-level-cache = <&l2_1>;
163 #cooling-cells = <2>;
164 };
165
166 cpu7: cpu@700 {
167 device_type = "cpu";
168 compatible = "arm,cortex-a78";
169 reg = <0x700>;
170 enable-method = "psci";
171 performance-domains = <&performance 1>;
172 clock-frequency = <2171000000>;
173 capacity-dmips-mhz = <1024>;
132 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
174 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
175 i-cache-size = <65536>;
176 i-cache-line-size = <64>;
177 i-cache-sets = <256>;
178 d-cache-size = <65536>;
179 d-cache-line-size = <64>;
180 d-cache-sets = <256>;
133 next-level-cache = <&l2_1>;
134 #cooling-cells = <2>;
135 };
136
137 cpu-map {
138 cluster0 {
139 core0 {
140 cpu = <&cpu0>;

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146
147 core2 {
148 cpu = <&cpu2>;
149 };
150
151 core3 {
152 cpu = <&cpu3>;
153 };
181 next-level-cache = <&l2_1>;
182 #cooling-cells = <2>;
183 };
184
185 cpu-map {
186 cluster0 {
187 core0 {
188 cpu = <&cpu0>;

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194
195 core2 {
196 cpu = <&cpu2>;
197 };
198
199 core3 {
200 cpu = <&cpu3>;
201 };
154 };
155
202
156 cluster1 {
157 core0 {
203 core4 {
158 cpu = <&cpu4>;
159 };
160
204 cpu = <&cpu4>;
205 };
206
161 core1 {
207 core5 {
162 cpu = <&cpu5>;
163 };
164
208 cpu = <&cpu5>;
209 };
210
165 core2 {
211 core6 {
166 cpu = <&cpu6>;
167 };
168
212 cpu = <&cpu6>;
213 };
214
169 core3 {
215 core7 {
170 cpu = <&cpu7>;
171 };
172 };
173 };
174
175 idle-states {
176 entry-method = "psci";
177
216 cpu = <&cpu7>;
217 };
218 };
219 };
220
221 idle-states {
222 entry-method = "psci";
223
178 cpu_off_l: cpu-off-l {
224 cpu_ret_l: cpu-retention-l {
179 compatible = "arm,idle-state";
180 arm,psci-suspend-param = <0x00010001>;
181 local-timer-stop;
182 entry-latency-us = <50>;
183 exit-latency-us = <95>;
184 min-residency-us = <580>;
185 };
186
225 compatible = "arm,idle-state";
226 arm,psci-suspend-param = <0x00010001>;
227 local-timer-stop;
228 entry-latency-us = <50>;
229 exit-latency-us = <95>;
230 min-residency-us = <580>;
231 };
232
187 cpu_off_b: cpu-off-b {
233 cpu_ret_b: cpu-retention-b {
188 compatible = "arm,idle-state";
189 arm,psci-suspend-param = <0x00010001>;
190 local-timer-stop;
191 entry-latency-us = <45>;
192 exit-latency-us = <140>;
193 min-residency-us = <740>;
194 };
195
234 compatible = "arm,idle-state";
235 arm,psci-suspend-param = <0x00010001>;
236 local-timer-stop;
237 entry-latency-us = <45>;
238 exit-latency-us = <140>;
239 min-residency-us = <740>;
240 };
241
196 cluster_off_l: cluster-off-l {
242 cpu_off_l: cpu-off-l {
197 compatible = "arm,idle-state";
198 arm,psci-suspend-param = <0x01010002>;
199 local-timer-stop;
200 entry-latency-us = <55>;
201 exit-latency-us = <155>;
202 min-residency-us = <840>;
203 };
204
243 compatible = "arm,idle-state";
244 arm,psci-suspend-param = <0x01010002>;
245 local-timer-stop;
246 entry-latency-us = <55>;
247 exit-latency-us = <155>;
248 min-residency-us = <840>;
249 };
250
205 cluster_off_b: cluster-off-b {
251 cpu_off_b: cpu-off-b {
206 compatible = "arm,idle-state";
207 arm,psci-suspend-param = <0x01010002>;
208 local-timer-stop;
209 entry-latency-us = <50>;
210 exit-latency-us = <200>;
211 min-residency-us = <1000>;
212 };
213 };
214
215 l2_0: l2-cache0 {
216 compatible = "cache";
217 cache-level = <2>;
252 compatible = "arm,idle-state";
253 arm,psci-suspend-param = <0x01010002>;
254 local-timer-stop;
255 entry-latency-us = <50>;
256 exit-latency-us = <200>;
257 min-residency-us = <1000>;
258 };
259 };
260
261 l2_0: l2-cache0 {
262 compatible = "cache";
263 cache-level = <2>;
264 cache-size = <131072>;
265 cache-line-size = <64>;
266 cache-sets = <512>;
218 next-level-cache = <&l3_0>;
219 };
220
221 l2_1: l2-cache1 {
222 compatible = "cache";
223 cache-level = <2>;
267 next-level-cache = <&l3_0>;
268 };
269
270 l2_1: l2-cache1 {
271 compatible = "cache";
272 cache-level = <2>;
273 cache-size = <262144>;
274 cache-line-size = <64>;
275 cache-sets = <512>;
224 next-level-cache = <&l3_0>;
225 };
226
227 l3_0: l3-cache {
228 compatible = "cache";
229 cache-level = <3>;
276 next-level-cache = <&l3_0>;
277 };
278
279 l3_0: l3-cache {
280 compatible = "cache";
281 cache-level = <3>;
282 cache-size = <2097152>;
283 cache-line-size = <64>;
284 cache-sets = <2048>;
285 cache-unified;
230 };
231 };
232
233 dsu-pmu {
234 compatible = "arm,dsu-pmu";
235 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
236 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
237 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;

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243 wakeup-delay-ms = <50>;
244 };
245
246 sound: mt8195-sound {
247 mediatek,platform = <&afe>;
248 status = "disabled";
249 };
250
286 };
287 };
288
289 dsu-pmu {
290 compatible = "arm,dsu-pmu";
291 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
292 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
293 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;

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299 wakeup-delay-ms = <50>;
300 };
301
302 sound: mt8195-sound {
303 mediatek,platform = <&afe>;
304 status = "disabled";
305 };
306
307 clk13m: fixed-factor-clock-13m {
308 compatible = "fixed-factor-clock";
309 #clock-cells = <0>;
310 clocks = <&clk26m>;
311 clock-div = <2>;
312 clock-mult = <1>;
313 clock-output-names = "clk13m";
314 };
315
251 clk26m: oscillator-26m {
252 compatible = "fixed-clock";
253 #clock-cells = <0>;
254 clock-frequency = <26000000>;
255 clock-output-names = "clk26m";
256 };
257
258 clk32k: oscillator-32k {

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682 mediatek,infracfg = <&infracfg_ao>;
683 #power-domain-cells = <0>;
684 };
685 };
686 };
687 };
688
689 watchdog: watchdog@10007000 {
316 clk26m: oscillator-26m {
317 compatible = "fixed-clock";
318 #clock-cells = <0>;
319 clock-frequency = <26000000>;
320 clock-output-names = "clk26m";
321 };
322
323 clk32k: oscillator-32k {

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747 mediatek,infracfg = <&infracfg_ao>;
748 #power-domain-cells = <0>;
749 };
750 };
751 };
752 };
753
754 watchdog: watchdog@10007000 {
690 compatible = "mediatek,mt8195-wdt",
691 "mediatek,mt6589-wdt";
755 compatible = "mediatek,mt8195-wdt";
692 mediatek,disable-extrst;
693 reg = <0 0x10007000 0 0x100>;
694 #reset-cells = <1>;
695 };
696
697 apmixedsys: syscon@1000c000 {
698 compatible = "mediatek,mt8195-apmixedsys", "syscon";
699 reg = <0 0x1000c000 0 0x1000>;
700 #clock-cells = <1>;
701 };
702
703 systimer: timer@10017000 {
704 compatible = "mediatek,mt8195-timer",
705 "mediatek,mt6765-timer";
706 reg = <0 0x10017000 0 0x1000>;
707 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
756 mediatek,disable-extrst;
757 reg = <0 0x10007000 0 0x100>;
758 #reset-cells = <1>;
759 };
760
761 apmixedsys: syscon@1000c000 {
762 compatible = "mediatek,mt8195-apmixedsys", "syscon";
763 reg = <0 0x1000c000 0 0x1000>;
764 #clock-cells = <1>;
765 };
766
767 systimer: timer@10017000 {
768 compatible = "mediatek,mt8195-timer",
769 "mediatek,mt6765-timer";
770 reg = <0 0x10017000 0 0x1000>;
771 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
708 clocks = <&topckgen CLK_TOP_CLK26M_D2>;
772 clocks = <&clk13m>;
709 };
710
711 pwrap: pwrap@10024000 {
712 compatible = "mediatek,mt8195-pwrap", "syscon";
713 reg = <0 0x10024000 0 0x1000>;
714 reg-names = "pwrap";
715 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
716 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,

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1041 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1042 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1043 clock-names = "spi";
1044 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1045 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1046 status = "disabled";
1047 };
1048
773 };
774
775 pwrap: pwrap@10024000 {
776 compatible = "mediatek,mt8195-pwrap", "syscon";
777 reg = <0 0x10024000 0 0x1000>;
778 reg-names = "pwrap";
779 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
780 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,

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1105 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1106 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1107 clock-names = "spi";
1108 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1109 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1110 status = "disabled";
1111 };
1112
1113 eth: ethernet@11021000 {
1114 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1115 reg = <0 0x11021000 0 0x4000>;
1116 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
1117 interrupt-names = "macirq";
1118 clock-names = "axi",
1119 "apb",
1120 "mac_main",
1121 "ptp_ref",
1122 "rmii_internal",
1123 "mac_cg";
1124 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
1125 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
1126 <&topckgen CLK_TOP_SNPS_ETH_250M>,
1127 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1128 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1129 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
1130 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1131 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1132 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
1133 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1134 <&topckgen CLK_TOP_ETHPLL_D8>,
1135 <&topckgen CLK_TOP_ETHPLL_D10>;
1136 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1137 mediatek,pericfg = <&infracfg_ao>;
1138 snps,axi-config = <&stmmac_axi_setup>;
1139 snps,mtl-rx-config = <&mtl_rx_setup>;
1140 snps,mtl-tx-config = <&mtl_tx_setup>;
1141 snps,txpbl = <16>;
1142 snps,rxpbl = <16>;
1143 snps,clk-csr = <0>;
1144 status = "disabled";
1145
1146 mdio {
1147 compatible = "snps,dwmac-mdio";
1148 #address-cells = <1>;
1149 #size-cells = <0>;
1150 };
1151
1152 stmmac_axi_setup: stmmac-axi-config {
1153 snps,wr_osr_lmt = <0x7>;
1154 snps,rd_osr_lmt = <0x7>;
1155 snps,blen = <0 0 0 0 16 8 4>;
1156 };
1157
1158 mtl_rx_setup: rx-queues-config {
1159 snps,rx-queues-to-use = <4>;
1160 snps,rx-sched-sp;
1161 queue0 {
1162 snps,dcb-algorithm;
1163 snps,map-to-dma-channel = <0x0>;
1164 };
1165 queue1 {
1166 snps,dcb-algorithm;
1167 snps,map-to-dma-channel = <0x0>;
1168 };
1169 queue2 {
1170 snps,dcb-algorithm;
1171 snps,map-to-dma-channel = <0x0>;
1172 };
1173 queue3 {
1174 snps,dcb-algorithm;
1175 snps,map-to-dma-channel = <0x0>;
1176 };
1177 };
1178
1179 mtl_tx_setup: tx-queues-config {
1180 snps,tx-queues-to-use = <4>;
1181 snps,tx-sched-wrr;
1182 queue0 {
1183 snps,weight = <0x10>;
1184 snps,dcb-algorithm;
1185 snps,priority = <0x0>;
1186 };
1187 queue1 {
1188 snps,weight = <0x11>;
1189 snps,dcb-algorithm;
1190 snps,priority = <0x1>;
1191 };
1192 queue2 {
1193 snps,weight = <0x12>;
1194 snps,dcb-algorithm;
1195 snps,priority = <0x2>;
1196 };
1197 queue3 {
1198 snps,weight = <0x13>;
1199 snps,dcb-algorithm;
1200 snps,priority = <0x3>;
1201 };
1202 };
1203 };
1204
1049 xhci0: usb@11200000 {
1050 compatible = "mediatek,mt8195-xhci",
1051 "mediatek,mtk-xhci";
1052 reg = <0 0x11200000 0 0x1000>,
1053 <0 0x11203e00 0 0x0100>;
1054 reg-names = "mac", "ippc";
1055 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1056 phys = <&u2port0 PHY_TYPE_USB2>,

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1253 <0x82000000 0 0x24200000
1254 0x0 0x24200000 0 0x3e00000>;
1255
1256 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1257 iommu-map-mask = <0x0>;
1258
1259 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
1260 <&clk26m>,
1205 xhci0: usb@11200000 {
1206 compatible = "mediatek,mt8195-xhci",
1207 "mediatek,mtk-xhci";
1208 reg = <0 0x11200000 0 0x1000>,
1209 <0 0x11203e00 0 0x0100>;
1210 reg-names = "mac", "ippc";
1211 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1212 phys = <&u2port0 PHY_TYPE_USB2>,

--- 196 unchanged lines hidden (view full) ---

1409 <0x82000000 0 0x24200000
1410 0x0 0x24200000 0 0x3e00000>;
1411
1412 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1413 iommu-map-mask = <0x0>;
1414
1415 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
1416 <&clk26m>,
1261 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
1417 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>,
1262 <&clk26m>,
1418 <&clk26m>,
1263 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
1419 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>,
1264 /* Designer has connect pcie1 with peri_mem_p0 clock */
1265 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1266 clock-names = "pl_250m", "tl_26m", "tl_96m",
1267 "tl_32k", "peri_26m", "peri_mem";
1268 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1269 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1270
1271 phys = <&u3port1 PHY_TYPE_PCIE>;

--- 103 unchanged lines hidden (view full) ---

1375 };
1376 pciephy_glb_intr: pciephy-glb-intr@193 {
1377 reg = <0x193 0x1>;
1378 bits = <0 4>;
1379 };
1380 dp_calibration: dp-data@1ac {
1381 reg = <0x1ac 0x10>;
1382 };
1420 /* Designer has connect pcie1 with peri_mem_p0 clock */
1421 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1422 clock-names = "pl_250m", "tl_26m", "tl_96m",
1423 "tl_32k", "peri_26m", "peri_mem";
1424 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1425 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1426
1427 phys = <&u3port1 PHY_TYPE_PCIE>;

--- 103 unchanged lines hidden (view full) ---

1531 };
1532 pciephy_glb_intr: pciephy-glb-intr@193 {
1533 reg = <0x193 0x1>;
1534 bits = <0 4>;
1535 };
1536 dp_calibration: dp-data@1ac {
1537 reg = <0x1ac 0x10>;
1538 };
1539 lvts_efuse_data1: lvts1-calib@1bc {
1540 reg = <0x1bc 0x14>;
1541 };
1542 lvts_efuse_data2: lvts2-calib@1d0 {
1543 reg = <0x1d0 0x38>;
1544 };
1383 };
1384
1385 u3phy2: t-phy@11c40000 {
1386 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1387 #address-cells = <1>;
1388 #size-cells = <1>;
1389 ranges = <0 0 0x11c40000 0x700>;
1390 status = "disabled";

--- 153 unchanged lines hidden (view full) ---

1544 #clock-cells = <1>;
1545 };
1546
1547 u3phy1: t-phy@11e30000 {
1548 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1549 #address-cells = <1>;
1550 #size-cells = <1>;
1551 ranges = <0 0 0x11e30000 0xe00>;
1545 };
1546
1547 u3phy2: t-phy@11c40000 {
1548 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1549 #address-cells = <1>;
1550 #size-cells = <1>;
1551 ranges = <0 0 0x11c40000 0x700>;
1552 status = "disabled";

--- 153 unchanged lines hidden (view full) ---

1706 #clock-cells = <1>;
1707 };
1708
1709 u3phy1: t-phy@11e30000 {
1710 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1711 #address-cells = <1>;
1712 #size-cells = <1>;
1713 ranges = <0 0 0x11e30000 0xe00>;
1714 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1552 status = "disabled";
1553
1554 u2port1: usb-phy@0 {
1555 reg = <0x0 0x700>;
1556 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1557 <&clk26m>;
1558 clock-names = "ref", "da_ref";
1559 #phy-cells = <1>;

--- 67 unchanged lines hidden (view full) ---

1627 };
1628
1629 mfgcfg: clock-controller@13fbf000 {
1630 compatible = "mediatek,mt8195-mfgcfg";
1631 reg = <0 0x13fbf000 0 0x1000>;
1632 #clock-cells = <1>;
1633 };
1634
1715 status = "disabled";
1716
1717 u2port1: usb-phy@0 {
1718 reg = <0x0 0x700>;
1719 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1720 <&clk26m>;
1721 clock-names = "ref", "da_ref";
1722 #phy-cells = <1>;

--- 67 unchanged lines hidden (view full) ---

1790 };
1791
1792 mfgcfg: clock-controller@13fbf000 {
1793 compatible = "mediatek,mt8195-mfgcfg";
1794 reg = <0 0x13fbf000 0 0x1000>;
1795 #clock-cells = <1>;
1796 };
1797
1635 vppsys0: clock-controller@14000000 {
1636 compatible = "mediatek,mt8195-vppsys0";
1798 vppsys0: syscon@14000000 {
1799 compatible = "mediatek,mt8195-vppsys0", "syscon";
1637 reg = <0 0x14000000 0 0x1000>;
1638 #clock-cells = <1>;
1639 };
1640
1641 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
1642 compatible = "mediatek,mt8195-smi-sub-common";
1643 reg = <0 0x14010000 0 0x1000>;
1644 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,

--- 87 unchanged lines hidden (view full) ---

1732 mediatek,smi = <&smi_common_vpp>;
1733 clocks = <&wpesys CLK_WPE_SMI_LARB8>,
1734 <&wpesys CLK_WPE_SMI_LARB8>,
1735 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
1736 clock-names = "apb", "smi", "gals";
1737 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
1738 };
1739
1800 reg = <0 0x14000000 0 0x1000>;
1801 #clock-cells = <1>;
1802 };
1803
1804 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
1805 compatible = "mediatek,mt8195-smi-sub-common";
1806 reg = <0 0x14010000 0 0x1000>;
1807 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,

--- 87 unchanged lines hidden (view full) ---

1895 mediatek,smi = <&smi_common_vpp>;
1896 clocks = <&wpesys CLK_WPE_SMI_LARB8>,
1897 <&wpesys CLK_WPE_SMI_LARB8>,
1898 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
1899 clock-names = "apb", "smi", "gals";
1900 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
1901 };
1902
1740 vppsys1: clock-controller@14f00000 {
1741 compatible = "mediatek,mt8195-vppsys1";
1903 vppsys1: syscon@14f00000 {
1904 compatible = "mediatek,mt8195-vppsys1", "syscon";
1742 reg = <0 0x14f00000 0 0x1000>;
1743 #clock-cells = <1>;
1744 };
1745
1746 larb5: larb@14f02000 {
1747 compatible = "mediatek,mt8195-smi-larb";
1748 reg = <0 0x14f02000 0 0x1000>;
1749 mediatek,larb-id = <5>;

--- 384 unchanged lines hidden (view full) ---

2134 assigned-clocks = <&topckgen CLK_TOP_VENC>;
2135 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2136 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2137 #address-cells = <2>;
2138 #size-cells = <2>;
2139 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
2140 };
2141
1905 reg = <0 0x14f00000 0 0x1000>;
1906 #clock-cells = <1>;
1907 };
1908
1909 larb5: larb@14f02000 {
1910 compatible = "mediatek,mt8195-smi-larb";
1911 reg = <0 0x14f02000 0 0x1000>;
1912 mediatek,larb-id = <5>;

--- 384 unchanged lines hidden (view full) ---

2297 assigned-clocks = <&topckgen CLK_TOP_VENC>;
2298 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2299 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2300 #address-cells = <2>;
2301 #size-cells = <2>;
2302 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
2303 };
2304
2305 jpgdec-master {
2306 compatible = "mediatek,mt8195-jpgdec";
2307 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2308 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
2309 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
2310 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
2311 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
2312 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
2313 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
2314 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
2315 #address-cells = <2>;
2316 #size-cells = <2>;
2317 ranges;
2318
2319 jpgdec@1a040000 {
2320 compatible = "mediatek,mt8195-jpgdec-hw";
2321 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
2322 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
2323 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
2324 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
2325 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
2326 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
2327 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
2328 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
2329 clocks = <&vencsys CLK_VENC_JPGDEC>;
2330 clock-names = "jpgdec";
2331 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2332 };
2333
2334 jpgdec@1a050000 {
2335 compatible = "mediatek,mt8195-jpgdec-hw";
2336 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
2337 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
2338 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
2339 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
2340 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
2341 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
2342 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
2343 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
2344 clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
2345 clock-names = "jpgdec";
2346 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2347 };
2348
2349 jpgdec@1b040000 {
2350 compatible = "mediatek,mt8195-jpgdec-hw";
2351 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
2352 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
2353 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
2354 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
2355 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
2356 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
2357 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
2358 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
2359 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
2360 clock-names = "jpgdec";
2361 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2362 };
2363 };
2364
2142 vencsys_core1: clock-controller@1b000000 {
2143 compatible = "mediatek,mt8195-vencsys_core1";
2144 reg = <0 0x1b000000 0 0x1000>;
2145 #clock-cells = <1>;
2146 };
2147
2148 vdosys0: syscon@1c01a000 {
2149 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
2150 reg = <0 0x1c01a000 0 0x1000>;
2151 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
2152 #clock-cells = <1>;
2153 };
2154
2365 vencsys_core1: clock-controller@1b000000 {
2366 compatible = "mediatek,mt8195-vencsys_core1";
2367 reg = <0 0x1b000000 0 0x1000>;
2368 #clock-cells = <1>;
2369 };
2370
2371 vdosys0: syscon@1c01a000 {
2372 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
2373 reg = <0 0x1c01a000 0 0x1000>;
2374 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
2375 #clock-cells = <1>;
2376 };
2377
2378
2379 jpgenc-master {
2380 compatible = "mediatek,mt8195-jpgenc";
2381 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2382 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
2383 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
2384 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
2385 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
2386 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
2387 #address-cells = <2>;
2388 #size-cells = <2>;
2389 ranges;
2390
2391 jpgenc@1a030000 {
2392 compatible = "mediatek,mt8195-jpgenc-hw";
2393 reg = <0 0x1a030000 0 0x10000>;
2394 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
2395 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
2396 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
2397 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
2398 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
2399 clocks = <&vencsys CLK_VENC_JPGENC>;
2400 clock-names = "jpgenc";
2401 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2402 };
2403
2404 jpgenc@1b030000 {
2405 compatible = "mediatek,mt8195-jpgenc-hw";
2406 reg = <0 0x1b030000 0 0x10000>;
2407 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
2408 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
2409 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
2410 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
2411 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
2412 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
2413 clock-names = "jpgenc";
2414 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2415 };
2416 };
2417
2155 larb20: larb@1b010000 {
2156 compatible = "mediatek,mt8195-smi-larb";
2157 reg = <0 0x1b010000 0 0x1000>;
2158 mediatek,larb-id = <20>;
2159 mediatek,smi = <&smi_common_vpp>;
2160 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
2161 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
2162 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;

--- 222 unchanged lines hidden --- 		2418 larb20: larb@1b010000 {
2419 compatible = "mediatek,mt8195-smi-larb";
2420 reg = <0 0x1b010000 0 0x1000>;
2421 mediatek,larb-id = <20>;
2422 mediatek,smi = <&smi_common_vpp>;
2423 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
2424 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
2425 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;

--- 222 unchanged lines hidden ---