mt8195.dtsi (2606cf059c56bfb86d5d6bd0f41bd7eedefc8b0a) mt8195.dtsi (d192615c307ec9f74cd0582880ece698533eb99b)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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308 };
309 };
310
311 dsu-pmu {
312 compatible = "arm,dsu-pmu";
313 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
314 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
315 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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308 };
309 };
310
311 dsu-pmu {
312 compatible = "arm,dsu-pmu";
313 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
314 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
315 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
316 status = "fail";
316 };
317
318 dmic_codec: dmic-codec {
319 compatible = "dmic-codec";
320 num-channels = <2>;
321 wakeup-delay-ms = <50>;
322 };
323

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2952 compatible = "mediatek,mt8195-disp-merge";
2953 reg = <0 0x1c10c000 0 0x1000>;
2954 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
2955 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
2956 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
2957 clock-names = "merge","merge_async";
2958 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2959 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
317 };
318
319 dmic_codec: dmic-codec {
320 compatible = "dmic-codec";
321 num-channels = <2>;
322 wakeup-delay-ms = <50>;
323 };
324

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2953 compatible = "mediatek,mt8195-disp-merge";
2954 reg = <0 0x1c10c000 0 0x1000>;
2955 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
2956 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
2957 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
2958 clock-names = "merge","merge_async";
2959 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2960 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
2960 mediatek,merge-mute;
2961 mediatek,merge-mute = <1>;
2961 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
2962 };
2963
2964 merge2: vpp-merge@1c10d000 {
2965 compatible = "mediatek,mt8195-disp-merge";
2966 reg = <0 0x1c10d000 0 0x1000>;
2967 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
2968 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
2969 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
2970 clock-names = "merge","merge_async";
2971 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2972 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
2962 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
2963 };
2964
2965 merge2: vpp-merge@1c10d000 {
2966 compatible = "mediatek,mt8195-disp-merge";
2967 reg = <0 0x1c10d000 0 0x1000>;
2968 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
2969 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
2970 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
2971 clock-names = "merge","merge_async";
2972 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2973 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
2973 mediatek,merge-mute;
2974 mediatek,merge-mute = <1>;
2974 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
2975 };
2976
2977 merge3: vpp-merge@1c10e000 {
2978 compatible = "mediatek,mt8195-disp-merge";
2979 reg = <0 0x1c10e000 0 0x1000>;
2980 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
2981 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
2982 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
2983 clock-names = "merge","merge_async";
2984 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2985 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
2975 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
2976 };
2977
2978 merge3: vpp-merge@1c10e000 {
2979 compatible = "mediatek,mt8195-disp-merge";
2980 reg = <0 0x1c10e000 0 0x1000>;
2981 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
2982 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
2983 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
2984 clock-names = "merge","merge_async";
2985 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2986 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
2986 mediatek,merge-mute;
2987 mediatek,merge-mute = <1>;
2987 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
2988 };
2989
2990 merge4: vpp-merge@1c10f000 {
2991 compatible = "mediatek,mt8195-disp-merge";
2992 reg = <0 0x1c10f000 0 0x1000>;
2993 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
2994 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
2995 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
2996 clock-names = "merge","merge_async";
2997 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2998 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
2988 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
2989 };
2990
2991 merge4: vpp-merge@1c10f000 {
2992 compatible = "mediatek,mt8195-disp-merge";
2993 reg = <0 0x1c10f000 0 0x1000>;
2994 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
2995 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
2996 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
2997 clock-names = "merge","merge_async";
2998 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2999 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
2999 mediatek,merge-mute;
3000 mediatek,merge-mute = <1>;
3000 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
3001 };
3002
3003 merge5: vpp-merge@1c110000 {
3004 compatible = "mediatek,mt8195-disp-merge";
3005 reg = <0 0x1c110000 0 0x1000>;
3006 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
3007 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
3008 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
3009 clock-names = "merge","merge_async";
3010 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3011 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3001 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
3002 };
3003
3004 merge5: vpp-merge@1c110000 {
3005 compatible = "mediatek,mt8195-disp-merge";
3006 reg = <0 0x1c110000 0 0x1000>;
3007 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
3008 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
3009 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
3010 clock-names = "merge","merge_async";
3011 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3012 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3012 mediatek,merge-fifo-en;
3013 mediatek,merge-fifo-en = <1>;
3013 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
3014 };
3015
3016 dp_intf1: dp-intf@1c113000 {
3017 compatible = "mediatek,mt8195-dp-intf";
3018 reg = <0 0x1c113000 0 0x1000>;
3019 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
3020 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;

--- 500 unchanged lines hidden --- 		3014 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
3015 };
3016
3017 dp_intf1: dp-intf@1c113000 {
3018 compatible = "mediatek,mt8195-dp-intf";
3019 reg = <0 0x1c113000 0 0x1000>;
3020 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
3021 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;

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