mt8195.dtsi (100c85421b52e41269ada88f7d71a6b8a06c7a11) mt8195.dtsi (96b0c1528ef41fe754f5d1378b1db6c098a2e33f)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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2023 reg = <0 0x13fbf000 0 0x1000>;
2024 #clock-cells = <1>;
2025 };
2026
2027 vppsys0: syscon@14000000 {
2028 compatible = "mediatek,mt8195-vppsys0", "syscon";
2029 reg = <0 0x14000000 0 0x1000>;
2030 #clock-cells = <1>;
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>

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2023 reg = <0 0x13fbf000 0 0x1000>;
2024 #clock-cells = <1>;
2025 };
2026
2027 vppsys0: syscon@14000000 {
2028 compatible = "mediatek,mt8195-vppsys0", "syscon";
2029 reg = <0 0x14000000 0 0x1000>;
2030 #clock-cells = <1>;
2031 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
2031 };
2032
2033 dma-controller@14001000 {
2034 compatible = "mediatek,mt8195-mdp3-rdma";
2035 reg = <0 0x14001000 0 0x1000>;
2036 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2037 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2038 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;

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2246 clock-names = "apb", "smi", "gals";
2247 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2248 };
2249
2250 vppsys1: syscon@14f00000 {
2251 compatible = "mediatek,mt8195-vppsys1", "syscon";
2252 reg = <0 0x14f00000 0 0x1000>;
2253 #clock-cells = <1>;
2032 };
2033
2034 dma-controller@14001000 {
2035 compatible = "mediatek,mt8195-mdp3-rdma";
2036 reg = <0 0x14001000 0 0x1000>;
2037 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2038 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2039 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;

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2247 clock-names = "apb", "smi", "gals";
2248 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2249 };
2250
2251 vppsys1: syscon@14f00000 {
2252 compatible = "mediatek,mt8195-vppsys1", "syscon";
2253 reg = <0 0x14f00000 0 0x1000>;
2254 #clock-cells = <1>;
2255 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
2254 };
2255
2256 mutex@14f01000 {
2257 compatible = "mediatek,mt8195-vpp-mutex";
2258 reg = <0 0x14f01000 0 0x1000>;
2259 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
2260 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2261 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;

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3075 #clock-cells = <1>;
3076 };
3077
3078 vdosys0: syscon@1c01a000 {
3079 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
3080 reg = <0 0x1c01a000 0 0x1000>;
3081 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
3082 #clock-cells = <1>;
2256 };
2257
2258 mutex@14f01000 {
2259 compatible = "mediatek,mt8195-vpp-mutex";
2260 reg = <0 0x14f01000 0 0x1000>;
2261 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
2262 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2263 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;

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3077 #clock-cells = <1>;
3078 };
3079
3080 vdosys0: syscon@1c01a000 {
3081 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
3082 reg = <0 0x1c01a000 0 0x1000>;
3083 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
3084 #clock-cells = <1>;
3085 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
3083 };
3084
3085
3086 jpgenc-master {
3087 compatible = "mediatek,mt8195-jpgenc";
3088 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3089 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
3090 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,

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3087
3088
3089 jpgenc-master {
3090 compatible = "mediatek,mt8195-jpgenc";
3091 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3092 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
3093 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,

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