| mt8195.dtsi (0d8eae7b124e2ddaee00f186fe922450faad0ed7) | mt8195.dtsi (1bd1d10d1c0cbb82ae42c5255821202e045e4c2b) |
|---|---|
| 1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> --- 1244 unchanged lines hidden (view full) --- 1253 <0x82000000 0 0x24200000 1254 0x0 0x24200000 0 0x3e00000>; 1255 1256 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1257 iommu-map-mask = <0x0>; 1258 1259 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1260 <&clk26m>, | 1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> --- 1244 unchanged lines hidden (view full) --- 1253 <0x82000000 0 0x24200000 1254 0x0 0x24200000 0 0x3e00000>; 1255 1256 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1257 iommu-map-mask = <0x0>; 1258 1259 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1260 <&clk26m>, |
| 1261 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, | 1261 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, |
| 1262 <&clk26m>, | 1262 <&clk26m>, |
| 1263 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, | 1263 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, |
| 1264 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1265 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1266 clock-names = "pl_250m", "tl_26m", "tl_96m", 1267 "tl_32k", "peri_26m", "peri_mem"; 1268 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1269 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1270 1271 phys = <&u3port1 PHY_TYPE_PCIE>; --- 1113 unchanged lines hidden --- | 1264 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1265 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1266 clock-names = "pl_250m", "tl_26m", "tl_96m", 1267 "tl_32k", "peri_26m", "peri_mem"; 1268 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1269 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1270 1271 phys = <&u3port1 PHY_TYPE_PCIE>; --- 1113 unchanged lines hidden --- |