mt8192.dtsi (53aa930dc4bae6aa269951bd37103083145d6691) mt8192.dtsi (6210fc2e4ca2551cb09fd122ee49ebcf64487f3e)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8192-clk.h>
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8192-clk.h>
9#include <dt-bindings/gce/mt8192-gce.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/memory/mt8192-larb-port.h>
12#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
13#include <dt-bindings/phy/phy.h>
14#include <dt-bindings/power/mt8192-power.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/memory/mt8192-larb-port.h>
13#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14#include <dt-bindings/phy/phy.h>
15#include <dt-bindings/power/mt8192-power.h>
16#include <dt-bindings/reset/mt8192-resets.h>
15
16/ {
17 compatible = "mediatek,mt8192";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
17
18/ {
19 compatible = "mediatek,mt8192";
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 aliases {
25 ovl0 = &ovl0;
26 ovl-2l0 = &ovl_2l0;
27 ovl-2l2 = &ovl_2l2;
28 rdma0 = &rdma0;
29 rdma4 = &rdma4;
30 };
31
22 clk26m: oscillator0 {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <26000000>;
26 clock-output-names = "clk26m";
27 };
28
29 clk32k: oscillator1 {

--- 271 unchanged lines hidden (view full) ---

301 #gpio-cells = <2>;
302 gpio-ranges = <&pio 0 0 220>;
303 interrupt-controller;
304 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
305 #interrupt-cells = <2>;
306 };
307
308 scpsys: syscon@10006000 {
32 clk26m: oscillator0 {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <26000000>;
36 clock-output-names = "clk26m";
37 };
38
39 clk32k: oscillator1 {

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311 #gpio-cells = <2>;
312 gpio-ranges = <&pio 0 0 220>;
313 interrupt-controller;
314 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
315 #interrupt-cells = <2>;
316 };
317
318 scpsys: syscon@10006000 {
309 compatible = "syscon", "simple-mfd";
319 compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd";
310 reg = <0 0x10006000 0 0x1000>;
320 reg = <0 0x10006000 0 0x1000>;
311 #power-domain-cells = <1>;
312
313 /* System Power Manager */
314 spm: power-controller {
315 compatible = "mediatek,mt8192-power-controller";
316 #address-cells = <1>;
317 #size-cells = <0>;
318 #power-domain-cells = <1>;
319

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548 <&topckgen CLK_TOP_SPMI_MST_SEL>;
549 clock-names = "pmif_sys_ck",
550 "pmif_tmr_ck",
551 "spmimst_clk_mux";
552 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
553 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
554 };
555
321
322 /* System Power Manager */
323 spm: power-controller {
324 compatible = "mediatek,mt8192-power-controller";
325 #address-cells = <1>;
326 #size-cells = <0>;
327 #power-domain-cells = <1>;
328

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557 <&topckgen CLK_TOP_SPMI_MST_SEL>;
558 clock-names = "pmif_sys_ck",
559 "pmif_tmr_ck",
560 "spmimst_clk_mux";
561 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
562 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
563 };
564
565 gce: mailbox@10228000 {
566 compatible = "mediatek,mt8192-gce";
567 reg = <0 0x10228000 0 0x4000>;
568 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
569 #mbox-cells = <2>;
570 clocks = <&infracfg CLK_INFRA_GCE>;
571 clock-names = "gce";
572 };
573
556 scp_adsp: clock-controller@10720000 {
557 compatible = "mediatek,mt8192-scp_adsp";
558 reg = <0 0x10720000 0 0x1000>;
559 #clock-cells = <1>;
560 };
561
562 uart0: serial@11002000 {
563 compatible = "mediatek,mt8192-uart",

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594 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
595 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
596 <&topckgen CLK_TOP_SPI_SEL>,
597 <&infracfg CLK_INFRA_SPI0>;
598 clock-names = "parent-clk", "sel-clk", "spi-clk";
599 status = "disabled";
600 };
601
574 scp_adsp: clock-controller@10720000 {
575 compatible = "mediatek,mt8192-scp_adsp";
576 reg = <0 0x10720000 0 0x1000>;
577 #clock-cells = <1>;
578 };
579
580 uart0: serial@11002000 {
581 compatible = "mediatek,mt8192-uart",

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612 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
613 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
614 <&topckgen CLK_TOP_SPI_SEL>,
615 <&infracfg CLK_INFRA_SPI0>;
616 clock-names = "parent-clk", "sel-clk", "spi-clk";
617 status = "disabled";
618 };
619
620 pwm0: pwm@1100e000 {
621 compatible = "mediatek,mt8183-disp-pwm";
622 reg = <0 0x1100e000 0 0x1000>;
623 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
624 #pwm-cells = <2>;
625 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
626 <&infracfg CLK_INFRA_DISP_PWM>;
627 clock-names = "main", "mm";
628 status = "disabled";
629 };
630
602 spi1: spi@11010000 {
603 compatible = "mediatek,mt8192-spi",
604 "mediatek,mt6765-spi";
605 #address-cells = <1>;
606 #size-cells = <0>;
607 reg = <0 0x11010000 0 0x1000>;
608 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
609 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,

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719 interrupt-names = "host";
720 phys = <&u2port0 PHY_TYPE_USB2>,
721 <&u3port0 PHY_TYPE_USB3>;
722 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
723 <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
724 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
725 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
726 clocks = <&infracfg CLK_INFRA_SSUSB>,
631 spi1: spi@11010000 {
632 compatible = "mediatek,mt8192-spi",
633 "mediatek,mt6765-spi";
634 #address-cells = <1>;
635 #size-cells = <0>;
636 reg = <0 0x11010000 0 0x1000>;
637 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
638 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,

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748 interrupt-names = "host";
749 phys = <&u2port0 PHY_TYPE_USB2>,
750 <&u3port0 PHY_TYPE_USB3>;
751 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
752 <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
753 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
754 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
755 clocks = <&infracfg CLK_INFRA_SSUSB>,
727 <&infracfg CLK_INFRA_SSUSB_XHCI>,
728 <&apmixedsys CLK_APMIXED_USBPLL>;
729 clock-names = "sys_ck", "xhci_ck", "ref_ck";
756 <&apmixedsys CLK_APMIXED_USBPLL>,
757 <&clk26m>,
758 <&clk26m>,
759 <&infracfg CLK_INFRA_SSUSB_XHCI>;
760 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
761 "xhci_ck";
730 wakeup-source;
731 mediatek,syscon-wakeup = <&pericfg 0x420 102>;
732 status = "disabled";
733 };
734
735 audsys: syscon@11210000 {
736 compatible = "mediatek,mt8192-audsys", "syscon";
737 reg = <0 0x11210000 0 0x2000>;

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1079 u3port0: usb-phy@700 {
1080 reg = <0x700 0x900>;
1081 clocks = <&clk26m>;
1082 clock-names = "ref";
1083 #phy-cells = <1>;
1084 };
1085 };
1086
762 wakeup-source;
763 mediatek,syscon-wakeup = <&pericfg 0x420 102>;
764 status = "disabled";
765 };
766
767 audsys: syscon@11210000 {
768 compatible = "mediatek,mt8192-audsys", "syscon";
769 reg = <0 0x11210000 0 0x2000>;

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1111 u3port0: usb-phy@700 {
1112 reg = <0x700 0x900>;
1113 clocks = <&clk26m>;
1114 clock-names = "ref";
1115 #phy-cells = <1>;
1116 };
1117 };
1118
1119 mipi_tx0: dsi-phy@11e50000 {
1120 compatible = "mediatek,mt8183-mipi-tx";
1121 reg = <0 0x11e50000 0 0x1000>;
1122 clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
1123 #clock-cells = <0>;
1124 #phy-cells = <0>;
1125 clock-output-names = "mipi_tx0_pll";
1126 status = "disabled";
1127 };
1128
1087 i2c0: i2c@11f00000 {
1088 compatible = "mediatek,mt8192-i2c";
1089 reg = <0 0x11f00000 0 0x1000>,
1090 <0 0x10217080 0 0x80>;
1091 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
1092 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
1093 <&infracfg CLK_INFRA_AP_DMA>;
1094 clock-names = "main", "dma";

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1161 reg = <0 0x13fbf000 0 0x1000>;
1162 #clock-cells = <1>;
1163 };
1164
1165 mmsys: syscon@14000000 {
1166 compatible = "mediatek,mt8192-mmsys", "syscon";
1167 reg = <0 0x14000000 0 0x1000>;
1168 #clock-cells = <1>;
1129 i2c0: i2c@11f00000 {
1130 compatible = "mediatek,mt8192-i2c";
1131 reg = <0 0x11f00000 0 0x1000>,
1132 <0 0x10217080 0 0x80>;
1133 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
1134 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
1135 <&infracfg CLK_INFRA_AP_DMA>;
1136 clock-names = "main", "dma";

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1203 reg = <0 0x13fbf000 0 0x1000>;
1204 #clock-cells = <1>;
1205 };
1206
1207 mmsys: syscon@14000000 {
1208 compatible = "mediatek,mt8192-mmsys", "syscon";
1209 reg = <0 0x14000000 0 0x1000>;
1210 #clock-cells = <1>;
1211 #reset-cells = <1>;
1212 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1213 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1214 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1169 };
1170
1215 };
1216
1217 mutex: mutex@14001000 {
1218 compatible = "mediatek,mt8192-disp-mutex";
1219 reg = <0 0x14001000 0 0x1000>;
1220 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
1221 clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1222 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1223 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
1224 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1225 };
1226
1171 smi_common: smi@14002000 {
1172 compatible = "mediatek,mt8192-smi-common";
1173 reg = <0 0x14002000 0 0x1000>;
1174 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1175 <&mmsys CLK_MM_SMI_INFRA>,
1176 <&mmsys CLK_MM_SMI_GALS>,
1177 <&mmsys CLK_MM_SMI_GALS>;
1178 clock-names = "apb", "smi", "gals0", "gals1";

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1194 reg = <0 0x14004000 0 0x1000>;
1195 mediatek,larb-id = <1>;
1196 mediatek,smi = <&smi_common>;
1197 clocks = <&clk26m>, <&clk26m>;
1198 clock-names = "apb", "smi";
1199 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1200 };
1201
1227 smi_common: smi@14002000 {
1228 compatible = "mediatek,mt8192-smi-common";
1229 reg = <0 0x14002000 0 0x1000>;
1230 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1231 <&mmsys CLK_MM_SMI_INFRA>,
1232 <&mmsys CLK_MM_SMI_GALS>,
1233 <&mmsys CLK_MM_SMI_GALS>;
1234 clock-names = "apb", "smi", "gals0", "gals1";

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1250 reg = <0 0x14004000 0 0x1000>;
1251 mediatek,larb-id = <1>;
1252 mediatek,smi = <&smi_common>;
1253 clocks = <&clk26m>, <&clk26m>;
1254 clock-names = "apb", "smi";
1255 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1256 };
1257
1258 ovl0: ovl@14005000 {
1259 compatible = "mediatek,mt8192-disp-ovl";
1260 reg = <0 0x14005000 0 0x1000>;
1261 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
1262 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1263 iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
1264 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
1265 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1266 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1267 };
1268
1269 ovl_2l0: ovl@14006000 {
1270 compatible = "mediatek,mt8192-disp-ovl-2l";
1271 reg = <0 0x14006000 0 0x1000>;
1272 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
1273 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1274 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1275 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
1276 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
1277 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1278 };
1279
1280 rdma0: rdma@14007000 {
1281 compatible = "mediatek,mt8192-disp-rdma",
1282 "mediatek,mt8183-disp-rdma";
1283 reg = <0 0x14007000 0 0x1000>;
1284 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
1285 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1286 iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
1287 mediatek,rdma-fifo-size = <5120>;
1288 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1289 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1290 };
1291
1292 color0: color@14009000 {
1293 compatible = "mediatek,mt8192-disp-color",
1294 "mediatek,mt8173-disp-color";
1295 reg = <0 0x14009000 0 0x1000>;
1296 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
1297 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1298 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1299 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1300 };
1301
1302 ccorr0: ccorr@1400a000 {
1303 compatible = "mediatek,mt8192-disp-ccorr";
1304 reg = <0 0x1400a000 0 0x1000>;
1305 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
1306 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1307 clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1308 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1309 };
1310
1311 aal0: aal@1400b000 {
1312 compatible = "mediatek,mt8192-disp-aal",
1313 "mediatek,mt8183-disp-aal";
1314 reg = <0 0x1400b000 0 0x1000>;
1315 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
1316 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1317 clocks = <&mmsys CLK_MM_DISP_AAL0>;
1318 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1319 };
1320
1321 gamma0: gamma@1400c000 {
1322 compatible = "mediatek,mt8192-disp-gamma",
1323 "mediatek,mt8183-disp-gamma";
1324 reg = <0 0x1400c000 0 0x1000>;
1325 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
1326 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1327 clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1328 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1329 };
1330
1331 postmask0: postmask@1400d000 {
1332 compatible = "mediatek,mt8192-disp-postmask";
1333 reg = <0 0x1400d000 0 0x1000>;
1334 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
1335 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1336 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
1337 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1338 };
1339
1340 dither0: dither@1400e000 {
1341 compatible = "mediatek,mt8192-disp-dither",
1342 "mediatek,mt8183-disp-dither";
1343 reg = <0 0x1400e000 0 0x1000>;
1344 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
1345 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1346 clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1347 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1348 };
1349
1350 dsi0: dsi@14010000 {
1351 compatible = "mediatek,mt8183-dsi";
1352 reg = <0 0x14010000 0 0x1000>;
1353 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
1354 clocks = <&mmsys CLK_MM_DSI0>,
1355 <&mmsys CLK_MM_DSI_DSI0>,
1356 <&mipi_tx0>;
1357 clock-names = "engine", "digital", "hs";
1358 phys = <&mipi_tx0>;
1359 phy-names = "dphy";
1360 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1361 resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
1362 status = "disabled";
1363
1364 port {
1365 dsi_out: endpoint { };
1366 };
1367 };
1368
1369 ovl_2l2: ovl@14014000 {
1370 compatible = "mediatek,mt8192-disp-ovl-2l";
1371 reg = <0 0x14014000 0 0x1000>;
1372 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
1373 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1374 clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
1375 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
1376 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
1377 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1378 };
1379
1380 rdma4: rdma@14015000 {
1381 compatible = "mediatek,mt8192-disp-rdma",
1382 "mediatek,mt8183-disp-rdma";
1383 reg = <0 0x14015000 0 0x1000>;
1384 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
1385 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1386 clocks = <&mmsys CLK_MM_DISP_RDMA4>;
1387 iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
1388 mediatek,rdma-fifo-size = <2048>;
1389 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1390 };
1391
1202 dpi0: dpi@14016000 {
1203 compatible = "mediatek,mt8192-dpi";
1204 reg = <0 0x14016000 0 0x1000>;
1205 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
1206 clocks = <&mmsys CLK_MM_DPI_DPI0>,
1207 <&mmsys CLK_MM_DISP_DPI0>,
1208 <&apmixedsys CLK_APMIXED_TVDPLL>;
1209 clock-names = "pixel", "engine", "pll";

--- 251 unchanged lines hidden --- 		1392 dpi0: dpi@14016000 {
1393 compatible = "mediatek,mt8192-dpi";
1394 reg = <0 0x14016000 0 0x1000>;
1395 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
1396 clocks = <&mmsys CLK_MM_DPI_DPI0>,
1397 <&mmsys CLK_MM_DISP_DPI0>,
1398 <&apmixedsys CLK_APMIXED_TVDPLL>;
1399 clock-names = "pixel", "engine", "pll";

--- 251 unchanged lines hidden ---