mt8183.dtsi (cac33c104a1007fb679011807c57553ac1288efe) mt8183.dtsi (251137b8fa97ef37ed7dadbed9de48475021fd8b)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
6 */
7
8#include <dt-bindings/clock/mt8183-clk.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include "mt8183-pinfunc.h"
12
13/ {
14 compatible = "mediatek,mt8183";
15 interrupt-parent = <&sysirq>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
6 */
7
8#include <dt-bindings/clock/mt8183-clk.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include "mt8183-pinfunc.h"
12
13/ {
14 compatible = "mediatek,mt8183";
15 interrupt-parent = <&sysirq>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 i2c0 = &i2c0;
21 i2c1 = &i2c1;
22 i2c2 = &i2c2;
23 i2c3 = &i2c3;
24 i2c4 = &i2c4;
25 i2c5 = &i2c5;
26 i2c6 = &i2c6;
27 i2c7 = &i2c7;
28 i2c8 = &i2c8;
29 i2c9 = &i2c9;
30 i2c10 = &i2c10;
31 i2c11 = &i2c11;
32 };
33
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu-map {
24 cluster0 {
25 core0 {
26 cpu = <&cpu0>;

--- 262 unchanged lines hidden (view full) ---

289 "mediatek,mt6577-uart";
290 reg = <0 0x11004000 0 0x1000>;
291 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
292 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
293 clock-names = "baud", "bus";
294 status = "disabled";
295 };
296
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu-map {
39 cluster0 {
40 core0 {
41 cpu = <&cpu0>;

--- 262 unchanged lines hidden (view full) ---

304 "mediatek,mt6577-uart";
305 reg = <0 0x11004000 0 0x1000>;
306 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
307 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
308 clock-names = "baud", "bus";
309 status = "disabled";
310 };
311
312 i2c6: i2c@11005000 {
313 compatible = "mediatek,mt8183-i2c";
314 reg = <0 0x11005000 0 0x1000>,
315 <0 0x11000600 0 0x80>;
316 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
317 clocks = <&infracfg CLK_INFRA_I2C6>,
318 <&infracfg CLK_INFRA_AP_DMA>;
319 clock-names = "main", "dma";
320 clock-div = <1>;
321 #address-cells = <1>;
322 #size-cells = <0>;
323 status = "disabled";
324 };
325
326 i2c0: i2c@11007000 {
327 compatible = "mediatek,mt8183-i2c";
328 reg = <0 0x11007000 0 0x1000>,
329 <0 0x11000080 0 0x80>;
330 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
331 clocks = <&infracfg CLK_INFRA_I2C0>,
332 <&infracfg CLK_INFRA_AP_DMA>;
333 clock-names = "main", "dma";
334 clock-div = <1>;
335 #address-cells = <1>;
336 #size-cells = <0>;
337 status = "disabled";
338 };
339
340 i2c4: i2c@11008000 {
341 compatible = "mediatek,mt8183-i2c";
342 reg = <0 0x11008000 0 0x1000>,
343 <0 0x11000100 0 0x80>;
344 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
345 clocks = <&infracfg CLK_INFRA_I2C1>,
346 <&infracfg CLK_INFRA_AP_DMA>,
347 <&infracfg CLK_INFRA_I2C1_ARBITER>;
348 clock-names = "main", "dma","arb";
349 clock-div = <1>;
350 #address-cells = <1>;
351 #size-cells = <0>;
352 status = "disabled";
353 };
354
355 i2c2: i2c@11009000 {
356 compatible = "mediatek,mt8183-i2c";
357 reg = <0 0x11009000 0 0x1000>,
358 <0 0x11000280 0 0x80>;
359 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
360 clocks = <&infracfg CLK_INFRA_I2C2>,
361 <&infracfg CLK_INFRA_AP_DMA>,
362 <&infracfg CLK_INFRA_I2C2_ARBITER>;
363 clock-names = "main", "dma", "arb";
364 clock-div = <1>;
365 #address-cells = <1>;
366 #size-cells = <0>;
367 status = "disabled";
368 };
369
297 spi0: spi@1100a000 {
298 compatible = "mediatek,mt8183-spi";
299 #address-cells = <1>;
300 #size-cells = <0>;
301 reg = <0 0x1100a000 0 0x1000>;
302 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
303 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
304 <&topckgen CLK_TOP_MUX_SPI>,
305 <&infracfg CLK_INFRA_SPI0>;
306 clock-names = "parent-clk", "sel-clk", "spi-clk";
307 status = "disabled";
308 };
309
370 spi0: spi@1100a000 {
371 compatible = "mediatek,mt8183-spi";
372 #address-cells = <1>;
373 #size-cells = <0>;
374 reg = <0 0x1100a000 0 0x1000>;
375 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
376 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
377 <&topckgen CLK_TOP_MUX_SPI>,
378 <&infracfg CLK_INFRA_SPI0>;
379 clock-names = "parent-clk", "sel-clk", "spi-clk";
380 status = "disabled";
381 };
382
383 i2c3: i2c@1100f000 {
384 compatible = "mediatek,mt8183-i2c";
385 reg = <0 0x1100f000 0 0x1000>,
386 <0 0x11000400 0 0x80>;
387 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
388 clocks = <&infracfg CLK_INFRA_I2C3>,
389 <&infracfg CLK_INFRA_AP_DMA>;
390 clock-names = "main", "dma";
391 clock-div = <1>;
392 #address-cells = <1>;
393 #size-cells = <0>;
394 status = "disabled";
395 };
396
310 spi1: spi@11010000 {
311 compatible = "mediatek,mt8183-spi";
312 #address-cells = <1>;
313 #size-cells = <0>;
314 reg = <0 0x11010000 0 0x1000>;
315 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
316 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
317 <&topckgen CLK_TOP_MUX_SPI>,
318 <&infracfg CLK_INFRA_SPI1>;
319 clock-names = "parent-clk", "sel-clk", "spi-clk";
320 status = "disabled";
321 };
322
397 spi1: spi@11010000 {
398 compatible = "mediatek,mt8183-spi";
399 #address-cells = <1>;
400 #size-cells = <0>;
401 reg = <0 0x11010000 0 0x1000>;
402 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
403 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
404 <&topckgen CLK_TOP_MUX_SPI>,
405 <&infracfg CLK_INFRA_SPI1>;
406 clock-names = "parent-clk", "sel-clk", "spi-clk";
407 status = "disabled";
408 };
409
410 i2c1: i2c@11011000 {
411 compatible = "mediatek,mt8183-i2c";
412 reg = <0 0x11011000 0 0x1000>,
413 <0 0x11000480 0 0x80>;
414 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
415 clocks = <&infracfg CLK_INFRA_I2C4>,
416 <&infracfg CLK_INFRA_AP_DMA>;
417 clock-names = "main", "dma";
418 clock-div = <1>;
419 #address-cells = <1>;
420 #size-cells = <0>;
421 status = "disabled";
422 };
423
323 spi2: spi@11012000 {
324 compatible = "mediatek,mt8183-spi";
325 #address-cells = <1>;
326 #size-cells = <0>;
327 reg = <0 0x11012000 0 0x1000>;
328 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
329 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
330 <&topckgen CLK_TOP_MUX_SPI>,

--- 10 unchanged lines hidden (view full) ---

341 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
342 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
343 <&topckgen CLK_TOP_MUX_SPI>,
344 <&infracfg CLK_INFRA_SPI3>;
345 clock-names = "parent-clk", "sel-clk", "spi-clk";
346 status = "disabled";
347 };
348
424 spi2: spi@11012000 {
425 compatible = "mediatek,mt8183-spi";
426 #address-cells = <1>;
427 #size-cells = <0>;
428 reg = <0 0x11012000 0 0x1000>;
429 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
430 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
431 <&topckgen CLK_TOP_MUX_SPI>,

--- 10 unchanged lines hidden (view full) ---

442 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
443 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
444 <&topckgen CLK_TOP_MUX_SPI>,
445 <&infracfg CLK_INFRA_SPI3>;
446 clock-names = "parent-clk", "sel-clk", "spi-clk";
447 status = "disabled";
448 };
449
450 i2c9: i2c@11014000 {
451 compatible = "mediatek,mt8183-i2c";
452 reg = <0 0x11014000 0 0x1000>,
453 <0 0x11000180 0 0x80>;
454 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
455 clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
456 <&infracfg CLK_INFRA_AP_DMA>,
457 <&infracfg CLK_INFRA_I2C1_ARBITER>;
458 clock-names = "main", "dma", "arb";
459 clock-div = <1>;
460 #address-cells = <1>;
461 #size-cells = <0>;
462 status = "disabled";
463 };
464
465 i2c10: i2c@11015000 {
466 compatible = "mediatek,mt8183-i2c";
467 reg = <0 0x11015000 0 0x1000>,
468 <0 0x11000300 0 0x80>;
469 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
470 clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
471 <&infracfg CLK_INFRA_AP_DMA>,
472 <&infracfg CLK_INFRA_I2C2_ARBITER>;
473 clock-names = "main", "dma", "arb";
474 clock-div = <1>;
475 #address-cells = <1>;
476 #size-cells = <0>;
477 status = "disabled";
478 };
479
480 i2c5: i2c@11016000 {
481 compatible = "mediatek,mt8183-i2c";
482 reg = <0 0x11016000 0 0x1000>,
483 <0 0x11000500 0 0x80>;
484 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
485 clocks = <&infracfg CLK_INFRA_I2C5>,
486 <&infracfg CLK_INFRA_AP_DMA>,
487 <&infracfg CLK_INFRA_I2C5_ARBITER>;
488 clock-names = "main", "dma", "arb";
489 clock-div = <1>;
490 #address-cells = <1>;
491 #size-cells = <0>;
492 status = "disabled";
493 };
494
495 i2c11: i2c@11017000 {
496 compatible = "mediatek,mt8183-i2c";
497 reg = <0 0x11017000 0 0x1000>,
498 <0 0x11000580 0 0x80>;
499 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
500 clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
501 <&infracfg CLK_INFRA_AP_DMA>,
502 <&infracfg CLK_INFRA_I2C5_ARBITER>;
503 clock-names = "main", "dma", "arb";
504 clock-div = <1>;
505 #address-cells = <1>;
506 #size-cells = <0>;
507 status = "disabled";
508 };
509
349 spi4: spi@11018000 {
350 compatible = "mediatek,mt8183-spi";
351 #address-cells = <1>;
352 #size-cells = <0>;
353 reg = <0 0x11018000 0 0x1000>;
354 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
355 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
356 <&topckgen CLK_TOP_MUX_SPI>,

--- 10 unchanged lines hidden (view full) ---

367 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
368 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
369 <&topckgen CLK_TOP_MUX_SPI>,
370 <&infracfg CLK_INFRA_SPI5>;
371 clock-names = "parent-clk", "sel-clk", "spi-clk";
372 status = "disabled";
373 };
374
510 spi4: spi@11018000 {
511 compatible = "mediatek,mt8183-spi";
512 #address-cells = <1>;
513 #size-cells = <0>;
514 reg = <0 0x11018000 0 0x1000>;
515 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
516 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
517 <&topckgen CLK_TOP_MUX_SPI>,

--- 10 unchanged lines hidden (view full) ---

528 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
529 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
530 <&topckgen CLK_TOP_MUX_SPI>,
531 <&infracfg CLK_INFRA_SPI5>;
532 clock-names = "parent-clk", "sel-clk", "spi-clk";
533 status = "disabled";
534 };
535
536 i2c7: i2c@1101a000 {
537 compatible = "mediatek,mt8183-i2c";
538 reg = <0 0x1101a000 0 0x1000>,
539 <0 0x11000680 0 0x80>;
540 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
541 clocks = <&infracfg CLK_INFRA_I2C7>,
542 <&infracfg CLK_INFRA_AP_DMA>;
543 clock-names = "main", "dma";
544 clock-div = <1>;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 status = "disabled";
548 };
549
550 i2c8: i2c@1101b000 {
551 compatible = "mediatek,mt8183-i2c";
552 reg = <0 0x1101b000 0 0x1000>,
553 <0 0x11000700 0 0x80>;
554 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
555 clocks = <&infracfg CLK_INFRA_I2C8>,
556 <&infracfg CLK_INFRA_AP_DMA>;
557 clock-names = "main", "dma";
558 clock-div = <1>;
559 #address-cells = <1>;
560 #size-cells = <0>;
561 status = "disabled";
562 };
563
375 audiosys: syscon@11220000 {
376 compatible = "mediatek,mt8183-audiosys", "syscon";
377 reg = <0 0x11220000 0 0x1000>;
378 #clock-cells = <1>;
379 };
380
381 efuse: efuse@11f10000 {
382 compatible = "mediatek,mt8183-efuse",

--- 65 unchanged lines hidden --- 		564 audiosys: syscon@11220000 {
565 compatible = "mediatek,mt8183-audiosys", "syscon";
566 reg = <0 0x11220000 0 0x1000>;
567 #clock-cells = <1>;
568 };
569
570 efuse: efuse@11f10000 {
571 compatible = "mediatek,mt8183-efuse",

--- 65 unchanged lines hidden ---