mt8167.dtsi (cdd38c5f1ce4398ec58fec95904b75824daab7b5) mt8167.dtsi (763e13f26894e3693ed9a72fbc796ed1e23c1e5b)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Copyright (c) 2020 BayLibre, SAS.
5 * Author: Fabien Parent <fparent@baylibre.com>
6 */
7
8#include <dt-bindings/clock/mt8167-clk.h>
9#include <dt-bindings/memory/mt8167-larb-port.h>
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Copyright (c) 2020 BayLibre, SAS.
5 * Author: Fabien Parent <fparent@baylibre.com>
6 */
7
8#include <dt-bindings/clock/mt8167-clk.h>
9#include <dt-bindings/memory/mt8167-larb-port.h>
10#include <dt-bindings/power/mt8167-power.h>
10
11#include "mt8167-pinfunc.h"
12
13#include "mt8516.dtsi"
14
15/ {
16 compatible = "mediatek,mt8167";
17

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29 };
30
31 apmixedsys: apmixedsys@10018000 {
32 compatible = "mediatek,mt8167-apmixedsys", "syscon";
33 reg = <0 0x10018000 0 0x710>;
34 #clock-cells = <1>;
35 };
36
11
12#include "mt8167-pinfunc.h"
13
14#include "mt8516.dtsi"
15
16/ {
17 compatible = "mediatek,mt8167";
18

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30 };
31
32 apmixedsys: apmixedsys@10018000 {
33 compatible = "mediatek,mt8167-apmixedsys", "syscon";
34 reg = <0 0x10018000 0 0x710>;
35 #clock-cells = <1>;
36 };
37
38 scpsys: syscon@10006000 {
39 compatible = "syscon", "simple-mfd";
40 reg = <0 0x10006000 0 0x1000>;
41 #power-domain-cells = <1>;
42
43 spm: power-controller {
44 compatible = "mediatek,mt8167-power-controller";
45 #address-cells = <1>;
46 #size-cells = <0>;
47 #power-domain-cells = <1>;
48
49 /* power domains of the SoC */
50 power-domain@MT8167_POWER_DOMAIN_MM {
51 reg = <MT8167_POWER_DOMAIN_MM>;
52 clocks = <&topckgen CLK_TOP_SMI_MM>;
53 clock-names = "mm";
54 #power-domain-cells = <0>;
55 mediatek,infracfg = <&infracfg>;
56 };
57
58 power-domain@MT8167_POWER_DOMAIN_VDEC {
59 reg = <MT8167_POWER_DOMAIN_VDEC>;
60 clocks = <&topckgen CLK_TOP_SMI_MM>,
61 <&topckgen CLK_TOP_RG_VDEC>;
62 clock-names = "mm", "vdec";
63 #power-domain-cells = <0>;
64 };
65
66 power-domain@MT8167_POWER_DOMAIN_ISP {
67 reg = <MT8167_POWER_DOMAIN_ISP>;
68 clocks = <&topckgen CLK_TOP_SMI_MM>;
69 clock-names = "mm";
70 #power-domain-cells = <0>;
71 };
72
73 power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
74 reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>;
75 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
76 <&topckgen CLK_TOP_RG_SLOW_MFG>;
77 clock-names = "axi_mfg", "mfg";
78 #address-cells = <1>;
79 #size-cells = <0>;
80 #power-domain-cells = <1>;
81 mediatek,infracfg = <&infracfg>;
82
83 power-domain@MT8167_POWER_DOMAIN_MFG_2D {
84 reg = <MT8167_POWER_DOMAIN_MFG_2D>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 #power-domain-cells = <1>;
88
89 power-domain@MT8167_POWER_DOMAIN_MFG {
90 reg = <MT8167_POWER_DOMAIN_MFG>;
91 #power-domain-cells = <0>;
92 mediatek,infracfg = <&infracfg>;
93 };
94 };
95 };
96
97 power-domain@MT8167_POWER_DOMAIN_CONN {
98 reg = <MT8167_POWER_DOMAIN_CONN>;
99 #power-domain-cells = <0>;
100 mediatek,infracfg = <&infracfg>;
101 };
102 };
103 };
104
37 imgsys: syscon@15000000 {
38 compatible = "mediatek,mt8167-imgsys", "syscon";
39 reg = <0 0x15000000 0 0x1000>;
40 #clock-cells = <1>;
41 };
42
43 vdecsys: syscon@16000000 {
44 compatible = "mediatek,mt8167-vdecsys", "syscon";

--- 17 unchanged lines hidden --- 		105 imgsys: syscon@15000000 {
106 compatible = "mediatek,mt8167-imgsys", "syscon";
107 reg = <0 0x15000000 0 0x1000>;
108 #clock-cells = <1>;
109 };
110
111 vdecsys: syscon@16000000 {
112 compatible = "mediatek,mt8167-vdecsys", "syscon";

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