mt8167.dtsi (97e37d44d35e14a74f989ec13d8587c37f3f0c75) mt8167.dtsi (e7ead62e2a1e574bf14b90dfcd2a74ba314a0c4d)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Copyright (c) 2020 BayLibre, SAS.
5 * Author: Fabien Parent <fparent@baylibre.com>
6 */
7
8#include <dt-bindings/clock/mt8167-clk.h>

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126 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
127 };
128
129 mmsys: mmsys@14000000 {
130 compatible = "mediatek,mt8167-mmsys", "syscon";
131 reg = <0 0x14000000 0 0x1000>;
132 #clock-cells = <1>;
133 };
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Copyright (c) 2020 BayLibre, SAS.
5 * Author: Fabien Parent <fparent@baylibre.com>
6 */
7
8#include <dt-bindings/clock/mt8167-clk.h>

--- 117 unchanged lines hidden (view full) ---

126 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
127 };
128
129 mmsys: mmsys@14000000 {
130 compatible = "mediatek,mt8167-mmsys", "syscon";
131 reg = <0 0x14000000 0 0x1000>;
132 #clock-cells = <1>;
133 };
134
135 smi_common: smi@14017000 {
136 compatible = "mediatek,mt8167-smi-common";
137 reg = <0 0x14017000 0 0x1000>;
138 clocks = <&mmsys CLK_MM_SMI_COMMON>,
139 <&mmsys CLK_MM_SMI_COMMON>;
140 clock-names = "apb", "smi";
141 power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
142 };
134 };
135};
143 };
144};