mt8167.dtsi (763e13f26894e3693ed9a72fbc796ed1e23c1e5b) mt8167.dtsi (97e37d44d35e14a74f989ec13d8587c37f3f0c75)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Copyright (c) 2020 BayLibre, SAS.
5 * Author: Fabien Parent <fparent@baylibre.com>
6 */
7
8#include <dt-bindings/clock/mt8167-clk.h>

--- 111 unchanged lines hidden (view full) ---

120 mediatek,pctl-regmap = <&syscfg_pctl>;
121 pins-are-numbered;
122 gpio-controller;
123 #gpio-cells = <2>;
124 interrupt-controller;
125 #interrupt-cells = <2>;
126 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
127 };
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Copyright (c) 2020 BayLibre, SAS.
5 * Author: Fabien Parent <fparent@baylibre.com>
6 */
7
8#include <dt-bindings/clock/mt8167-clk.h>

--- 111 unchanged lines hidden (view full) ---

120 mediatek,pctl-regmap = <&syscfg_pctl>;
121 pins-are-numbered;
122 gpio-controller;
123 #gpio-cells = <2>;
124 interrupt-controller;
125 #interrupt-cells = <2>;
126 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
127 };
128
129 mmsys: mmsys@14000000 {
130 compatible = "mediatek,mt8167-mmsys", "syscon";
131 reg = <0 0x14000000 0 0x1000>;
132 #clock-cells = <1>;
133 };
128 };
129};
134 };
135};