mt8167.dtsi (585a78c1f77be305b1f6adad392f16047fb66ffd) mt8167.dtsi (404200964b24b19fe93325d24811f59a2a8b4de7)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Copyright (c) 2020 BayLibre, SAS.
5 * Author: Fabien Parent <fparent@baylibre.com>
6 */
7
8#include <dt-bindings/clock/mt8167-clk.h>

--- 110 unchanged lines hidden (view full) ---

119 mediatek,pctl-regmap = <&syscfg_pctl>;
120 gpio-controller;
121 #gpio-cells = <2>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
125 };
126
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Copyright (c) 2020 BayLibre, SAS.
5 * Author: Fabien Parent <fparent@baylibre.com>
6 */
7
8#include <dt-bindings/clock/mt8167-clk.h>

--- 110 unchanged lines hidden (view full) ---

119 mediatek,pctl-regmap = <&syscfg_pctl>;
120 gpio-controller;
121 #gpio-cells = <2>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
125 };
126
127 mmsys: mmsys@14000000 {
127 mmsys: syscon@14000000 {
128 compatible = "mediatek,mt8167-mmsys", "syscon";
129 reg = <0 0x14000000 0 0x1000>;
130 #clock-cells = <1>;
131 };
132
133 smi_common: smi@14017000 {
134 compatible = "mediatek,mt8167-smi-common";
135 reg = <0 0x14017000 0 0x1000>;

--- 45 unchanged lines hidden --- 		128 compatible = "mediatek,mt8167-mmsys", "syscon";
129 reg = <0 0x14000000 0 0x1000>;
130 #clock-cells = <1>;
131 };
132
133 smi_common: smi@14017000 {
134 compatible = "mediatek,mt8167-smi-common";
135 reg = <0 0x14017000 0 0x1000>;

--- 45 unchanged lines hidden ---