mt7986a.dtsi (e21cbfc3d93177069260552b4706ba8def759030) mt7986a.dtsi (513b49d19b34cf7bec4bc0e6284df2aa9007e88d)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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341 "dma_ck",
342 "xhci_ck";
343 phys = <&u2port0 PHY_TYPE_USB2>,
344 <&u3port0 PHY_TYPE_USB3>,
345 <&u2port1 PHY_TYPE_USB2>;
346 status = "disabled";
347 };
348
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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341 "dma_ck",
342 "xhci_ck";
343 phys = <&u2port0 PHY_TYPE_USB2>,
344 <&u3port0 PHY_TYPE_USB3>,
345 <&u2port1 PHY_TYPE_USB2>;
346 status = "disabled";
347 };
348
349 mmc0: mmc@11230000 {
350 compatible = "mediatek,mt7986-mmc";
351 reg = <0 0x11230000 0 0x1000>,
352 <0 0x11c20000 0 0x1000>;
353 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
355 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
356 <&infracfg CLK_INFRA_MSDC_CK>,
357 <&infracfg CLK_INFRA_MSDC_133M_CK>,
358 <&infracfg CLK_INFRA_MSDC_66M_CK>;
359 clock-names = "source", "hclk", "source_cg", "bus_clk",
360 "sys_cg";
361 status = "disabled";
362 };
363
349 usb_phy: t-phy@11e10000 {
350 compatible = "mediatek,mt7986-tphy",
351 "mediatek,generic-tphy-v2";
352 #address-cells = <1>;
353 #size-cells = <1>;
354 ranges = <0 0 0x11e10000 0x1700>;
355 status = "disabled";
356

--- 135 unchanged lines hidden --- 		364 usb_phy: t-phy@11e10000 {
365 compatible = "mediatek,mt7986-tphy",
366 "mediatek,generic-tphy-v2";
367 #address-cells = <1>;
368 #size-cells = <1>;
369 ranges = <0 0 0x11e10000 0x1700>;
370 status = "disabled";
371

--- 135 unchanged lines hidden ---