mt7986a.dtsi (a108772d03d8bdb43258218b00bfe43bbe1e8800) mt7986a.dtsi (300218b0503d40f3efc69363ca70b7f75c3ba81f)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/mt7986-clk.h>
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/mt7986-clk.h>
10#include <dt-bindings/reset/mt7986-resets.h>
10
11/ {
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 clk40m: oscillator@0 {
17 compatible = "fixed-clock";

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65 #address-cells = <2>;
66 #size-cells = <2>;
67 ranges;
68 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
69 secmon_reserved: secmon@43000000 {
70 reg = <0 0x43000000 0 0x30000>;
71 no-map;
72 };
11
12/ {
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 clk40m: oscillator@0 {
18 compatible = "fixed-clock";

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66 #address-cells = <2>;
67 #size-cells = <2>;
68 ranges;
69 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
70 secmon_reserved: secmon@43000000 {
71 reg = <0 0x43000000 0 0x30000>;
72 no-map;
73 };
74
75 wmcpu_emi: wmcpu-reserved@4fc00000 {
76 no-map;
77 reg = <0 0x4fc00000 0 0x00100000>;
78 };
73 };
74
75 timer {
76 compatible = "arm,armv8-timer";
77 interrupt-parent = <&gic>;
78 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
79 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
80 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,

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256 <&apmixedsys CLK_APMIXED_SGMPLL>;
257 mediatek,ethsys = <&ethsys>;
258 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
259 #reset-cells = <1>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 status = "disabled";
263 };
79 };
80
81 timer {
82 compatible = "arm,armv8-timer";
83 interrupt-parent = <&gic>;
84 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
85 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
86 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,

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262 <&apmixedsys CLK_APMIXED_SGMPLL>;
263 mediatek,ethsys = <&ethsys>;
264 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
265 #reset-cells = <1>;
266 #address-cells = <1>;
267 #size-cells = <0>;
268 status = "disabled";
269 };
270
271 wifi: wifi@18000000 {
272 compatible = "mediatek,mt7986-wmac";
273 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
274 reset-names = "consys";
275 clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
276 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
277 clock-names = "mcu", "ap2conn";
278 reg = <0 0x18000000 0 0x1000000>,
279 <0 0x10003000 0 0x1000>,
280 <0 0x11d10000 0 0x1000>;
281 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
285 memory-region = <&wmcpu_emi>;
286 };
264 };
265
266};
287 };
288
289};