mt7986a.dtsi (50137c150f5f478e083b0b24b650de49f55ebfa2) mt7986a.dtsi (c3a064a32ed98437dd62ff30e07a4ea3c659852f)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 93 unchanged lines hidden (view full) ---

102 compatible = "mediatek,mt7986-wdt",
103 "mediatek,mt6589-wdt";
104 reg = <0 0x1001c000 0 0x1000>;
105 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
106 #reset-cells = <1>;
107 status = "disabled";
108 };
109
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 93 unchanged lines hidden (view full) ---

102 compatible = "mediatek,mt7986-wdt",
103 "mediatek,mt6589-wdt";
104 reg = <0 0x1001c000 0 0x1000>;
105 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
106 #reset-cells = <1>;
107 status = "disabled";
108 };
109
110 pio: pinctrl@1001f000 {
111 compatible = "mediatek,mt7986a-pinctrl";
112 reg = <0 0x1001f000 0 0x1000>,
113 <0 0x11c30000 0 0x1000>,
114 <0 0x11c40000 0 0x1000>,
115 <0 0x11e20000 0 0x1000>,
116 <0 0x11e30000 0 0x1000>,
117 <0 0x11f00000 0 0x1000>,
118 <0 0x11f10000 0 0x1000>,
119 <0 0x1000b000 0 0x1000>;
120 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
121 "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
122 gpio-controller;
123 #gpio-cells = <2>;
124 gpio-ranges = <&pio 0 0 100>;
125 interrupt-controller;
126 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
127 interrupt-parent = <&gic>;
128 #interrupt-cells = <2>;
129 };
130
110 trng: trng@1020f000 {
111 compatible = "mediatek,mt7986-rng",
112 "mediatek,mt7623-rng";
113 reg = <0 0x1020f000 0 0x100>;
114 clocks = <&system_clk>;
115 clock-names = "rng";
116 status = "disabled";
117 };

--- 31 unchanged lines hidden --- 		131 trng: trng@1020f000 {
132 compatible = "mediatek,mt7986-rng",
133 "mediatek,mt7623-rng";
134 reg = <0 0x1020f000 0 0x100>;
135 clocks = <&system_clk>;
136 clock-names = "rng";
137 status = "disabled";
138 };

--- 31 unchanged lines hidden ---