mt7986a.dtsi (407da561244b9d51e6a794d6305ba38ec2c9d907) mt7986a.dtsi (e21cbfc3d93177069260552b4706ba8def759030)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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318 clocks = <&topckgen CLK_TOP_MPLL_D2>,
319 <&topckgen CLK_TOP_SPIM_MST_SEL>,
320 <&infracfg CLK_INFRA_SPI1_CK>,
321 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
322 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
323 status = "disabled";
324 };
325
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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318 clocks = <&topckgen CLK_TOP_MPLL_D2>,
319 <&topckgen CLK_TOP_SPIM_MST_SEL>,
320 <&infracfg CLK_INFRA_SPI1_CK>,
321 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
322 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
323 status = "disabled";
324 };
325
326 ssusb: usb@11200000 {
327 compatible = "mediatek,mt7986-xhci",
328 "mediatek,mtk-xhci";
329 reg = <0 0x11200000 0 0x2e00>,
330 <0 0x11203e00 0 0x0100>;
331 reg-names = "mac", "ippc";
332 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
334 <&infracfg CLK_INFRA_IUSB_CK>,
335 <&infracfg CLK_INFRA_IUSB_133_CK>,
336 <&infracfg CLK_INFRA_IUSB_66M_CK>,
337 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
338 clock-names = "sys_ck",
339 "ref_ck",
340 "mcu_ck",
341 "dma_ck",
342 "xhci_ck";
343 phys = <&u2port0 PHY_TYPE_USB2>,
344 <&u3port0 PHY_TYPE_USB3>,
345 <&u2port1 PHY_TYPE_USB2>;
346 status = "disabled";
347 };
348
349 usb_phy: t-phy@11e10000 {
350 compatible = "mediatek,mt7986-tphy",
351 "mediatek,generic-tphy-v2";
352 #address-cells = <1>;
353 #size-cells = <1>;
354 ranges = <0 0 0x11e10000 0x1700>;
355 status = "disabled";
356
357 u2port0: usb-phy@0 {
358 reg = <0x0 0x700>;
359 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
360 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
361 clock-names = "ref", "da_ref";
362 #phy-cells = <1>;
363 };
364
365 u3port0: usb-phy@700 {
366 reg = <0x700 0x900>;
367 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
368 clock-names = "ref";
369 #phy-cells = <1>;
370 };
371
372 u2port1: usb-phy@1000 {
373 reg = <0x1000 0x700>;
374 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
375 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
376 clock-names = "ref", "da_ref";
377 #phy-cells = <1>;
378 };
379 };
380
326 ethsys: syscon@15000000 {
327 #address-cells = <1>;
328 #size-cells = <1>;
329 compatible = "mediatek,mt7986-ethsys",
330 "syscon";
331 reg = <0 0x15000000 0 0x1000>;
332 #clock-cells = <1>;
333 #reset-cells = <1>;

--- 103 unchanged lines hidden --- 		381 ethsys: syscon@15000000 {
382 #address-cells = <1>;
383 #size-cells = <1>;
384 compatible = "mediatek,mt7986-ethsys",
385 "syscon";
386 reg = <0 0x15000000 0 0x1000>;
387 #clock-cells = <1>;
388 #reset-cells = <1>;

--- 103 unchanged lines hidden ---