mt7986a.dtsi (0aea30a07ec6b50de0fc5f5b2ec34a68ead86b61) mt7986a.dtsi (082ff36bd5c010f77227d881a199c7548f0a6aaf)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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217 #size-cells = <1>;
218 compatible = "mediatek,mt7986-ethsys",
219 "syscon";
220 reg = <0 0x15000000 0 0x1000>;
221 #clock-cells = <1>;
222 #reset-cells = <1>;
223 };
224
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 208 unchanged lines hidden (view full) ---

217 #size-cells = <1>;
218 compatible = "mediatek,mt7986-ethsys",
219 "syscon";
220 reg = <0 0x15000000 0 0x1000>;
221 #clock-cells = <1>;
222 #reset-cells = <1>;
223 };
224
225 eth: ethernet@15100000 {
226 compatible = "mediatek,mt7986-eth";
227 reg = <0 0x15100000 0 0x80000>;
228 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&ethsys CLK_ETH_FE_EN>,
233 <&ethsys CLK_ETH_GP2_EN>,
234 <&ethsys CLK_ETH_GP1_EN>,
235 <&ethsys CLK_ETH_WOCPU1_EN>,
236 <&ethsys CLK_ETH_WOCPU0_EN>,
237 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
238 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
239 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
240 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
241 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
242 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
243 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
244 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
245 <&topckgen CLK_TOP_NETSYS_SEL>,
246 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
247 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
248 "sgmii_tx250m", "sgmii_rx250m",
249 "sgmii_cdr_ref", "sgmii_cdr_fb",
250 "sgmii2_tx250m", "sgmii2_rx250m",
251 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
252 "netsys0", "netsys1";
253 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
254 <&topckgen CLK_TOP_SGM_325M_SEL>;
255 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
256 <&apmixedsys CLK_APMIXED_SGMPLL>;
257 mediatek,ethsys = <&ethsys>;
258 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
259 #reset-cells = <1>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 status = "disabled";
263 };
225 };
226
227};
264 };
265
266};