mt7986a.dtsi (002c6ca75289a4ac4f6738213dd2d258704886e4) mt7986a.dtsi (2658963084567eb9505292470d40f7322006a69a)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/mt7986-clk.h>
10#include <dt-bindings/reset/mt7986-resets.h>
11
12/ {
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/mt7986-clk.h>
10#include <dt-bindings/reset/mt7986-resets.h>
11
12/ {
13 compatible = "mediatek,mt7986a";
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 clk40m: oscillator@0 {
18 compatible = "fixed-clock";
19 clock-frequency = <40000000>;
20 #clock-cells = <0>;

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163
164 sgmiisys1: syscon@10070000 {
165 compatible = "mediatek,mt7986-sgmiisys_1",
166 "syscon";
167 reg = <0 0x10070000 0 0x1000>;
168 #clock-cells = <1>;
169 };
170
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 clk40m: oscillator@0 {
19 compatible = "fixed-clock";
20 clock-frequency = <40000000>;
21 #clock-cells = <0>;

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164
165 sgmiisys1: syscon@10070000 {
166 compatible = "mediatek,mt7986-sgmiisys_1",
167 "syscon";
168 reg = <0 0x10070000 0 0x1000>;
169 #clock-cells = <1>;
170 };
171
171 trng: trng@1020f000 {
172 trng: rng@1020f000 {
172 compatible = "mediatek,mt7986-rng",
173 "mediatek,mt7623-rng";
174 reg = <0 0x1020f000 0 0x100>;
175 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
176 clock-names = "rng";
177 status = "disabled";
178 };
179
173 compatible = "mediatek,mt7986-rng",
174 "mediatek,mt7623-rng";
175 reg = <0 0x1020f000 0 0x100>;
176 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
177 clock-names = "rng";
178 status = "disabled";
179 };
180
181 crypto: crypto@10320000 {
182 compatible = "inside-secure,safexcel-eip97";
183 reg = <0 0x10320000 0 0x40000>;
184 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
188 interrupt-names = "ring0", "ring1", "ring2", "ring3";
189 clocks = <&infracfg CLK_INFRA_EIP97_CK>;
190 clock-names = "infra_eip97_ck";
191 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
192 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
193 status = "disabled";
194 };
195
180 uart0: serial@11002000 {
181 compatible = "mediatek,mt7986-uart",
182 "mediatek,mt6577-uart";
183 reg = <0 0x11002000 0 0x400>;
184 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
186 <&infracfg CLK_INFRA_UART0_CK>;
187 clock-names = "baud", "bus";

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213 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
214 <&infracfg CLK_INFRA_UART2_CK>;
215 clock-names = "baud", "bus";
216 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
217 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
218 status = "disabled";
219 };
220
196 uart0: serial@11002000 {
197 compatible = "mediatek,mt7986-uart",
198 "mediatek,mt6577-uart";
199 reg = <0 0x11002000 0 0x400>;
200 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
202 <&infracfg CLK_INFRA_UART0_CK>;
203 clock-names = "baud", "bus";

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229 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
230 <&infracfg CLK_INFRA_UART2_CK>;
231 clock-names = "baud", "bus";
232 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
233 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
234 status = "disabled";
235 };
236
237 i2c0: i2c@11008000 {
238 compatible = "mediatek,mt7986-i2c";
239 reg = <0 0x11008000 0 0x90>,
240 <0 0x10217080 0 0x80>;
241 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
242 clock-div = <5>;
243 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
244 <&infracfg CLK_INFRA_AP_DMA_CK>;
245 clock-names = "main", "dma";
246 #address-cells = <1>;
247 #size-cells = <0>;
248 status = "disabled";
249 };
250
221 ethsys: syscon@15000000 {
222 #address-cells = <1>;
223 #size-cells = <1>;
224 compatible = "mediatek,mt7986-ethsys",
225 "syscon";
226 reg = <0 0x15000000 0 0x1000>;
227 #clock-cells = <1>;
228 #reset-cells = <1>;

--- 85 unchanged lines hidden --- 		251 ethsys: syscon@15000000 {
252 #address-cells = <1>;
253 #size-cells = <1>;
254 compatible = "mediatek,mt7986-ethsys",
255 "syscon";
256 reg = <0 0x15000000 0 0x1000>;
257 #clock-cells = <1>;
258 #reset-cells = <1>;

--- 85 unchanged lines hidden ---