hi6220.dtsi (cd0b69ec0eb5e489954d7125b934457ac7acf6f7) hi6220.dtsi (6485160396fcec2fa8a0acfa7c8c090f020db694)
1/*
2 * dts file for Hisilicon Hi6220 SoC
3 *
4 * Copyright (C) 2015, Hisilicon Ltd.
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/clock/hi6220-clock.h>

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78 };
79 };
80
81 cpu0: cpu@0 {
82 compatible = "arm,cortex-a53", "arm,armv8";
83 device_type = "cpu";
84 reg = <0x0 0x0>;
85 enable-method = "psci";
1/*
2 * dts file for Hisilicon Hi6220 SoC
3 *
4 * Copyright (C) 2015, Hisilicon Ltd.
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/clock/hi6220-clock.h>

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78 };
79 };
80
81 cpu0: cpu@0 {
82 compatible = "arm,cortex-a53", "arm,armv8";
83 device_type = "cpu";
84 reg = <0x0 0x0>;
85 enable-method = "psci";
86 next-level-cache = <&CLUSTER0_L2>;
86 clocks = <&stub_clock 0>;
87 operating-points-v2 = <&cpu_opp_table>;
88 cooling-min-level = <4>;
89 cooling-max-level = <0>;
90 #cooling-cells = <2>; /* min followed by max */
91 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
92 dynamic-power-coefficient = <311>;
93 };
94
95 cpu1: cpu@1 {
96 compatible = "arm,cortex-a53", "arm,armv8";
97 device_type = "cpu";
98 reg = <0x0 0x1>;
99 enable-method = "psci";
87 clocks = <&stub_clock 0>;
88 operating-points-v2 = <&cpu_opp_table>;
89 cooling-min-level = <4>;
90 cooling-max-level = <0>;
91 #cooling-cells = <2>; /* min followed by max */
92 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
93 dynamic-power-coefficient = <311>;
94 };
95
96 cpu1: cpu@1 {
97 compatible = "arm,cortex-a53", "arm,armv8";
98 device_type = "cpu";
99 reg = <0x0 0x1>;
100 enable-method = "psci";
101 next-level-cache = <&CLUSTER0_L2>;
100 operating-points-v2 = <&cpu_opp_table>;
101 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
102 };
103
104 cpu2: cpu@2 {
105 compatible = "arm,cortex-a53", "arm,armv8";
106 device_type = "cpu";
107 reg = <0x0 0x2>;
108 enable-method = "psci";
102 operating-points-v2 = <&cpu_opp_table>;
103 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
104 };
105
106 cpu2: cpu@2 {
107 compatible = "arm,cortex-a53", "arm,armv8";
108 device_type = "cpu";
109 reg = <0x0 0x2>;
110 enable-method = "psci";
111 next-level-cache = <&CLUSTER0_L2>;
109 operating-points-v2 = <&cpu_opp_table>;
110 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
111 };
112
113 cpu3: cpu@3 {
114 compatible = "arm,cortex-a53", "arm,armv8";
115 device_type = "cpu";
116 reg = <0x0 0x3>;
117 enable-method = "psci";
112 operating-points-v2 = <&cpu_opp_table>;
113 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
114 };
115
116 cpu3: cpu@3 {
117 compatible = "arm,cortex-a53", "arm,armv8";
118 device_type = "cpu";
119 reg = <0x0 0x3>;
120 enable-method = "psci";
121 next-level-cache = <&CLUSTER0_L2>;
118 operating-points-v2 = <&cpu_opp_table>;
119 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
120 };
121
122 cpu4: cpu@100 {
123 compatible = "arm,cortex-a53", "arm,armv8";
124 device_type = "cpu";
125 reg = <0x0 0x100>;
126 enable-method = "psci";
122 operating-points-v2 = <&cpu_opp_table>;
123 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
124 };
125
126 cpu4: cpu@100 {
127 compatible = "arm,cortex-a53", "arm,armv8";
128 device_type = "cpu";
129 reg = <0x0 0x100>;
130 enable-method = "psci";
131 next-level-cache = <&CLUSTER1_L2>;
127 operating-points-v2 = <&cpu_opp_table>;
128 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
129 };
130
131 cpu5: cpu@101 {
132 compatible = "arm,cortex-a53", "arm,armv8";
133 device_type = "cpu";
134 reg = <0x0 0x101>;
135 enable-method = "psci";
132 operating-points-v2 = <&cpu_opp_table>;
133 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
134 };
135
136 cpu5: cpu@101 {
137 compatible = "arm,cortex-a53", "arm,armv8";
138 device_type = "cpu";
139 reg = <0x0 0x101>;
140 enable-method = "psci";
141 next-level-cache = <&CLUSTER1_L2>;
136 operating-points-v2 = <&cpu_opp_table>;
137 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
138 };
139
140 cpu6: cpu@102 {
141 compatible = "arm,cortex-a53", "arm,armv8";
142 device_type = "cpu";
143 reg = <0x0 0x102>;
144 enable-method = "psci";
142 operating-points-v2 = <&cpu_opp_table>;
143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 };
145
146 cpu6: cpu@102 {
147 compatible = "arm,cortex-a53", "arm,armv8";
148 device_type = "cpu";
149 reg = <0x0 0x102>;
150 enable-method = "psci";
151 next-level-cache = <&CLUSTER1_L2>;
145 operating-points-v2 = <&cpu_opp_table>;
146 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
147 };
148
149 cpu7: cpu@103 {
150 compatible = "arm,cortex-a53", "arm,armv8";
151 device_type = "cpu";
152 reg = <0x0 0x103>;
153 enable-method = "psci";
152 operating-points-v2 = <&cpu_opp_table>;
153 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
154 };
155
156 cpu7: cpu@103 {
157 compatible = "arm,cortex-a53", "arm,armv8";
158 device_type = "cpu";
159 reg = <0x0 0x103>;
160 enable-method = "psci";
161 next-level-cache = <&CLUSTER1_L2>;
154 operating-points-v2 = <&cpu_opp_table>;
155 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
156 };
162 operating-points-v2 = <&cpu_opp_table>;
163 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
164 };
165
166 CLUSTER0_L2: l2-cache0 {
167 compatible = "cache";
168 };
169
170 CLUSTER1_L2: l2-cache1 {
171 compatible = "cache";
172 };
157 };
158
159 cpu_opp_table: cpu_opp_table {
160 compatible = "operating-points-v2";
161 opp-shared;
162
163 opp00 {
164 opp-hz = /bits/ 64 <208000000>;

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174
175 cpu_opp_table: cpu_opp_table {
176 compatible = "operating-points-v2";
177 opp-shared;
178
179 opp00 {
180 opp-hz = /bits/ 64 <208000000>;

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