hi6220.dtsi (01b944fe1cd4e21a2a9ed51adbdbafe2d5e905ba) hi6220.dtsi (a362ec8f677e5d701bc587edad93128897748c32)
1/*
2 * dts file for Hisilicon Hi6220 SoC
3 *
4 * Copyright (C) 2015, Hisilicon Ltd.
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
1/*
2 * dts file for Hisilicon Hi6220 SoC
3 *
4 * Copyright (C) 2015, Hisilicon Ltd.
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/clock/hi6220-clock.h>
8
9/ {
10 compatible = "hisilicon,hi6220";
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 psci {

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159 reg = <0x0 0xf7032000 0x0 0x1000>;
160 #clock-cells = <1>;
161 };
162
163 uart0: uart@f8015000 { /* console */
164 compatible = "arm,pl011", "arm,primecell";
165 reg = <0x0 0xf8015000 0x0 0x1000>;
166 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
9
10/ {
11 compatible = "hisilicon,hi6220";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 psci {

--- 143 unchanged lines hidden (view full) ---

160 reg = <0x0 0xf7032000 0x0 0x1000>;
161 #clock-cells = <1>;
162 };
163
164 uart0: uart@f8015000 { /* console */
165 compatible = "arm,pl011", "arm,primecell";
166 reg = <0x0 0xf8015000 0x0 0x1000>;
167 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
168 clocks = <&ao_ctrl HI6220_UART0_PCLK>,
169 <&ao_ctrl HI6220_UART0_PCLK>;
168 clock-names = "uartclk", "apb_pclk";
169 };
170 clock-names = "uartclk", "apb_pclk";
171 };
172
173 uart1: uart@f7111000 {
174 compatible = "arm,pl011", "arm,primecell";
175 reg = <0x0 0xf7111000 0x0 0x1000>;
176 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
178 <&sys_ctrl HI6220_UART1_PCLK>;
179 clock-names = "uartclk", "apb_pclk";
180 status = "disabled";
181 };
182
183 uart2: uart@f7112000 {
184 compatible = "arm,pl011", "arm,primecell";
185 reg = <0x0 0xf7112000 0x0 0x1000>;
186 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
188 <&sys_ctrl HI6220_UART2_PCLK>;
189 clock-names = "uartclk", "apb_pclk";
190 status = "disabled";
191 };
192
193 uart3: uart@f7113000 {
194 compatible = "arm,pl011", "arm,primecell";
195 reg = <0x0 0xf7113000 0x0 0x1000>;
196 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
198 <&sys_ctrl HI6220_UART3_PCLK>;
199 clock-names = "uartclk", "apb_pclk";
200 };
201
202 uart4: uart@f7114000 {
203 compatible = "arm,pl011", "arm,primecell";
204 reg = <0x0 0xf7114000 0x0 0x1000>;
205 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
207 <&sys_ctrl HI6220_UART4_PCLK>;
208 clock-names = "uartclk", "apb_pclk";
209 status = "disabled";
210 };
170 };
171};
211 };
212};