hi3798cv200.dtsi (8dd06ef34b6e2f41b29fbf5fc1663780f2524285) hi3798cv200.dtsi (8c563f55ee1d0241b834dd4b43be11cf7a47732b)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * DTS File for HiSilicon Hi3798cv200 SoC.
4 *
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
6 */
7
8#include <dt-bindings/clock/histb-clock.h>

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86 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
87 reg = <0x8a22000 0x1000>;
88 #clock-cells = <1>;
89 #reset-cells = <2>;
90
91 gmacphyrst: reset-controller {
92 compatible = "ti,syscon-reset";
93 #reset-cells = <1>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * DTS File for HiSilicon Hi3798cv200 SoC.
4 *
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
6 */
7
8#include <dt-bindings/clock/histb-clock.h>

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86 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
87 reg = <0x8a22000 0x1000>;
88 #clock-cells = <1>;
89 #reset-cells = <2>;
90
91 gmacphyrst: reset-controller {
92 compatible = "ti,syscon-reset";
93 #reset-cells = <1>;
94 ti,reset-bits =
95 <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
96 DEASSERT_SET|STATUS_NONE)>,
97 <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
98 DEASSERT_SET|STATUS_NONE)>;
94 ti,reset-bits = <
95 0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)
96 0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)
97 >;
99 };
100 };
101
102 sysctrl: system-controller@8000000 {
103 compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
104 reg = <0x8000000 0x1000>;
105 #clock-cells = <1>;
106 #reset-cells = <2>;

--- 514 unchanged lines hidden --- 		98 };
99 };
100
101 sysctrl: system-controller@8000000 {
102 compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
103 reg = <0x8000000 0x1000>;
104 #clock-cells = <1>;
105 #reset-cells = <2>;

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