hi3670.dtsi (c00e3f8080d1ad8645ba51ae34817df830b44fa2) hi3670.dtsi (a758dd2e3a5108ab84c33c1069dd838f866b014e)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3670 SoC
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 * Copyright (C) 2018, Linaro Ltd.
7 */
8

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182 };
183
184 media2_crg: media2_crgctrl@e8900000 {
185 compatible = "hisilicon,hi3670-media2-crg","syscon";
186 reg = <0x0 0xe8900000 0x0 0x1000>;
187 #clock-cells = <1>;
188 };
189
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3670 SoC
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 * Copyright (C) 2018, Linaro Ltd.
7 */
8

--- 173 unchanged lines hidden (view full) ---

182 };
183
184 media2_crg: media2_crgctrl@e8900000 {
185 compatible = "hisilicon,hi3670-media2-crg","syscon";
186 reg = <0x0 0xe8900000 0x0 0x1000>;
187 #clock-cells = <1>;
188 };
189
190 uart6_clk: clk_19_2M {
191 compatible = "fixed-clock";
192 #clock-cells = <0>;
193 clock-frequency = <19200000>;
194 };
195
196 uart6: serial@fff32000 {
197 compatible = "arm,pl011", "arm,primecell";
198 reg = <0x0 0xfff32000 0x0 0x1000>;
199 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
190 uart6: serial@fff32000 {
191 compatible = "arm,pl011", "arm,primecell";
192 reg = <0x0 0xfff32000 0x0 0x1000>;
193 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&uart6_clk &uart6_clk>;
194 clocks = <&crg_ctrl HI3670_CLK_UART6>,
195 <&crg_ctrl HI3670_PCLK>;
201 clock-names = "uartclk", "apb_pclk";
202 status = "disabled";
203 };
204 };
205};
196 clock-names = "uartclk", "apb_pclk";
197 status = "disabled";
198 };
199 };
200};