hi3670.dtsi (9b0dcd0e5a27958b57e3e390f63c098d63a055da) hi3670.dtsi (ddd0dc915647f12b5cbfa0a5e7d65389dcd71771)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3670 SoC
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 * Copyright (C) 2018, Linaro Ltd.
7 */
8

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146 ranges;
147
148 crg_ctrl: crg_ctrl@fff35000 {
149 compatible = "hisilicon,hi3670-crgctrl", "syscon";
150 reg = <0x0 0xfff35000 0x0 0x1000>;
151 #clock-cells = <1>;
152 };
153
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3670 SoC
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 * Copyright (C) 2018, Linaro Ltd.
7 */
8

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146 ranges;
147
148 crg_ctrl: crg_ctrl@fff35000 {
149 compatible = "hisilicon,hi3670-crgctrl", "syscon";
150 reg = <0x0 0xfff35000 0x0 0x1000>;
151 #clock-cells = <1>;
152 };
153
154 crg_rst: crg_rst_controller {
155 compatible = "hisilicon,hi3670-reset",
156 "hisilicon,hi3660-reset";
157 #reset-cells = <2>;
158 hisi,rst-syscon = <&crg_ctrl>;
159 };
160
154 pctrl: pctrl@e8a09000 {
155 compatible = "hisilicon,hi3670-pctrl", "syscon";
156 reg = <0x0 0xe8a09000 0x0 0x1000>;
157 #clock-cells = <1>;
158 };
159
160 pmuctrl: crg_ctrl@fff34000 {
161 compatible = "hisilicon,hi3670-pmuctrl", "syscon";

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642 gpio-controller;
643 #gpio-cells = <2>;
644 gpio-ranges = <&pmx1 1 35 7>;
645 interrupt-controller;
646 #interrupt-cells = <2>;
647 clocks = <&sctrl HI3670_PCLK_AO_GPIO6>;
648 clock-names = "apb_pclk";
649 };
161 pctrl: pctrl@e8a09000 {
162 compatible = "hisilicon,hi3670-pctrl", "syscon";
163 reg = <0x0 0xe8a09000 0x0 0x1000>;
164 #clock-cells = <1>;
165 };
166
167 pmuctrl: crg_ctrl@fff34000 {
168 compatible = "hisilicon,hi3670-pmuctrl", "syscon";

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649 gpio-controller;
650 #gpio-cells = <2>;
651 gpio-ranges = <&pmx1 1 35 7>;
652 interrupt-controller;
653 #interrupt-cells = <2>;
654 clocks = <&sctrl HI3670_PCLK_AO_GPIO6>;
655 clock-names = "apb_pclk";
656 };
657
658 /* UFS */
659 ufs: ufs@ff3c0000 {
660 compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
661 /* 0: HCI standard */
662 /* 1: UFS SYS CTRL */
663 reg = <0x0 0xff3c0000 0x0 0x1000>,
664 <0x0 0xff3e0000 0x0 0x1000>;
665 interrupt-parent = <&gic>;
666 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
668 <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
669 clock-names = "ref_clk", "phy_clk";
670 freq-table-hz = <0 0>, <0 0>;
671 /* offset: 0x84; bit: 12 */
672 resets = <&crg_rst 0x84 12>;
673 reset-names = "rst";
674 };
675
676 /* SD */
677 dwmmc1: dwmmc1@ff37f000 {
678 compatible = "hisilicon,hi3670-dw-mshc",
679 "hisilicon,hi3660-dw-mshc";
680 reg = <0x0 0xff37f000 0x0 0x1000>;
681 #address-cells = <1>;
682 #size-cells = <0>;
683 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&crg_ctrl HI3670_CLK_GATE_SD>,
685 <&crg_ctrl HI3670_HCLK_GATE_SD>;
686 clock-names = "ciu", "biu";
687 clock-frequency = <3200000>;
688 resets = <&crg_rst 0x94 18>;
689 reset-names = "reset";
690 hisilicon,peripheral-syscon = <&sctrl>;
691 card-detect-delay = <200>;
692 status = "disabled";
693 };
694
695 /* SDIO */
696 dwmmc2: dwmmc2@fc183000 {
697 compatible = "hisilicon,hi3670-dw-mshc",
698 "hisilicon,hi3660-dw-mshc";
699 reg = <0x0 0xfc183000 0x0 0x1000>;
700 #address-cells = <1>;
701 #size-cells = <0>;
702 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&crg_ctrl HI3670_CLK_GATE_SDIO>,
704 <&crg_ctrl HI3670_HCLK_GATE_SDIO>;
705 clock-names = "ciu", "biu";
706 clock-frequency = <3200000>;
707 resets = <&crg_rst 0x94 20>;
708 reset-names = "reset";
709 card-detect-delay = <200>;
710 status = "disabled";
711 };
650 };
651};
712 };
713};